1. Fall 2006 1 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Computer Organization Lecture 8 Detailed MIPS datapath Timing overview

2. Fall 2006 2 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Project 2 overview Sixteen-bit ALU Use four LS181 plus some other logic Arithmetic: +, - Logical: –and, or –shift left, shift right

3. Fall 2006 3 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Project 2 hints Use four LS181’s ALU Design shifter circuits Use muxes to select between ALU and shifters Design combinational logic to control muxes: consider a ROM

4. Fall 2006 4 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Project 2 questions?

5. Fall 2006 5 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering MIPS datapath overview Instruction read from memory Registers selected for operation ALU performs function Result written to register

6. Fall 2006 6 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Shift register review

7. Fall 2006 7 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Shift register operation Clock & Reset connected/bused to each flip-flop With Sin = 1, data moves left-to-right on each clock edge (1000, 1100, 1110, 1111) We could modify the design –32-bit shift register –Add combinational logic between flip-flops

8. Fall 2006 8 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering MIPS datapath Information moves left-to-right

9. Fall 2006 9 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Key elements of datapath Shared memory: instructions and data Single ALU –PC increment by 4 –Functions: +, -, and, or, etc. –Determines effective & branch/jump addresses Temporary registers: hold data between clock edges (like shift register does)

10. Fall 2006 10 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering New temporary registers Instruction (IR): holds current instruction Memory data (MDR): holds data read from memory A, B: holds data from register file ALUout: holds ALU output (Project 2) Note: All of these are D-type flip-flops

11. Fall 2006 11 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering MIPS datapath Data travels left-to-right on each clock edge Clock Driver Clock 1 Clock 2 Clock 3 Clock 4 Clock 5

12. Fall 2006 12 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Example timing Instruction fetch Instruction decode, register read Execution Memory access Register write 12345 Instructions vary from 3 – 5 clocks

13. Fall 2006 13 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Complete the table? Instruction Total Clocks Clock 12345 add $1, $2, $34xxxx beq $1, $2, label4xxx lw $1, offset ($2)5xxxxx sub $1, $2, $34xxxx sw $1, offset ($2)4xxxx j label3xxx 1 = Instruction Fetch 2 = Decode & Register Read 3 = Execution 4 = Memory Access 5 = Register Write

14. Fall 2006 14 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Datapath organization detail Five muxes select between various sources 1 2 3 4 5

15. Fall 2006 15 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Muxes added 1.Address for memory: PC or ALU 2.Write register: rs or rt 3.Write data: memory, ALU 4.ALU first operand: PC, Register 1 5.ALU second operand: Register 2, 0x4, sign extended, sign extended shifted 2

16. Fall 2006 16 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Timing parameters D flip-flop has setup and propagation delays t su t prop D input Clock Q output Q Q D C

17. Fall 2006 17 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Synchronous logic Clock period > T prop + T comb + T set Edge-triggered logic Register

18. Fall 2006 18 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Find the F max ? Mem = 20 ns; Reg = 15 ns; ALU = 55 ns Assume: mem, reg, ALU dominant terms

19. Fall 2006 19 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Now add controller signals

20. Fall 2006 20 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering What do these signals do? SignalFunction? IorDControls address of memory: PC, ALU MemReadPuts memory in read mode MemWritePuts memory in write mode IRWriteWrite data to instruction register RegDstRs or rt for register write data RegWritePuts registers in write mode

21. Fall 2006 21 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering What do these signals do? SignalFunction? ALUSrcAData for A input of ALU ALUOpFunction code for ALU ALUSrcBData for B input of ALU MemtoRegData for the register write: memory, ALU

22. Fall 2006 22 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Branch and jump additions Next PC value, three possible sources –PC+4: ALU output –Branch target: ALUout register –Jump address: concatenation of PC 31-28, IR 25-0 shifted left 2, two lsb of zero PC write control –PCWrite: unconditional (increments, jump) –PCWriteCond: conditional write for branch

23. Fall 2006 23 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Complete datapath new

24. Fall 2006 24 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Datapath and controller Controller Input

25. Fall 2006 25 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering

26. Fall 2006 26 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Complete the table? Instruction Total Clocks Clock 12345 add $1, $2, $34xxxx beq $1, $2, label3xxx lw $1, offset ($2)5xxxxx sub $1, $2, $33xxxx sw $1, offset ($2)4xxxx j label3xxx 1 = Instruction Fetch 2 = Decode & Register Read 3 = Execution 4 = Memory Access 5 = Register Write

27. Fall 2006 27 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering Find the F max ? Mem = 20 ns;Reg = 15 ns; ALU = 55 ns F max = 1/55ns = 18.1 MHz Assume: mem, reg, ALU dominant terms 20 ns 15 ns 55 ns

28. Fall 2006 28 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering What do these signals do? SignalFunction? IorDControls address of memory: PC, ALU MemReadPuts memory in read mode MemWriteData written to memory IRWriteData written to IR RegDstSelects rs or rt for register write RegWriteData written to register file

29. Fall 2006 29 EE 333 Lillevik 333f06-l8 University of Portland School of Engineering What do these signals do? SignalFunction? ALUSrcADetermines ALU first operand ALUOpDefines ALU function (+, -, etc.) ALUSrcBDetermines ALU second operand MemtoRegMemory or ALU is data for register write