1. Fall 2006 1 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Computer Organization Lecture 13 Controller implementations Register file design MDP16 overview

2. Fall 2006 2 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Controller and datapath Inputs IR(31:25) Outputs

3. Fall 2006 3 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Full FSM state diagram Inputs:Op Outputs: 13 signals States: 10

4. Fall 2006 4 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering FSM architecture Present State NS Decoder Output Decoder Inputs Outputs Combo logic ROM MUX Combo logic ROM MUX Decoder Flip Flops

5. Fall 2006 5 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering FSM controller State register (D- type FF) holds present state (PS)

6. Fall 2006 6 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering PLA implementation State (PS) bits and Op determine outputs and next state Alternately, use a ROM IN OUT NS PS

7. Fall 2006 7 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Project 4: Register File Two, 16-bit registers ($0, $1) Two read ports One write port Equal output

8. Fall 2006 8 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Inputs InputFunction ResetForces the output to all zeros. CLKSynchronous clock for entire MDP16 design. DinPort with 16-bit number to load into register file. REGrdDefines read port contents 00 R1 = $0, R0 = $0 01 R1 = $0, R0 = $1 10 R1 = $1, R0 = $0 11 R1 = $1, R0 = $1 REGwrDefines destination register for writes 00Disable write port 01Write to register $0 10Write to register $1 11Write to register $1, $0 (both registers)

9. Fall 2006 9 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Outputs OutputFunction R0outRead port zero (R0), 16-bits R1outRead port one (R1), 16-bits EQStatus bit that indicates R0 and R1 contain identical numbers $0Register $0 output for debugging, 16-bits $1Register $1 output for debugging, 16-bits

10. Fall 2006 10 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Register design Read ports Write port

11. Fall 2006 11 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering MDP16 overview Architecture similar to MIPS Sixteen-bit machine Two registers: $0, $1 Word addressing (0x0000 – 0xffff) Memory: 0xffff = 2 16 = 65,536 words Formats: R, I, J-types

12. Fall 2006 12 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering MDP16 schematic

13. Fall 2006 13 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering MDP16 schematic

14. Fall 2006 14 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Instruction format opadr 0 111215 op rsrtadr/imm 1215111090 I J R op rsrt funcrd 1215111090 3 0 84

15. Fall 2006 15 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Basic questions Why do we have just two registers? What is the most positive and negative address offset? What is the range of the jump address?

16. Fall 2006 16 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Instructions NameOpFormatFuncExampleMeaning add sub addi subi and or andi ori sll srl 11AB11CD2311AB11CD23 RRIIRRIIIIRRIIRRIIII 0 1 na 2 3 na add $0, $0, $1 sub $0, $0, $1 addi $0, $1, 20 subi $0, $1, 20 and $0, $0, $1 or $0, $0, $1 andi $0, $1, 1f ori $0, $1, 1f sll $0, $1 srl $0, $1 $0 = $0 + $1 $0 = $0 - $1 $0 = $1 + 20 $0 = $1 - 20 $0 = $0 & $1 $0 = $0 || $1 $0 = $1 & 1f $0 = $1 || 1f $0 = $1 << 1 bit $0 = $1 >> 1 bit

17. Fall 2006 17 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Instructions, continued. NameOpFormatExampleMeaning nop lw sw beq j resv 0 4 5 6 7 8,9 E,F J I J NA nop lw $0, c3 ($1) sw $0, c3 ($1) beq $0, $1, 2a j 23 NA No operation $0 = mem [$1 + c3] mem [$1 + c3] = $0 If ($0 == $1) go to (PC + 1) + 2a PC = PC [15- 12] || 23 NA

18. Fall 2006 18 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Find machine instruction? InstructionTypeOp rsrtrdimmed /adr functMachine (hex) add $0, $0, $1 r0001010na00000x1400 andi $0, $1, 10f I11000110f0xc50f sll $0, $1 i0010010x2400 lw $0, 323 ($1) I010010143ten0x4a11 beq $0, $1, 17a j a64

19. Fall 2006 19 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering MDP16 programming We do not have an assembler –Must “hand” assemble –Limited to small programs – Senior design project anyone? Assume the MIPS syntax, addressing, directives, labels

20. Fall 2006 20 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Simple program

21. Fall 2006 21 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Assemble the simple program? AddressMachine Instruction Assembly Instruction Comment 0000x1001 sub $0, $0, $0 # $0 = 0 0010x1e01 sub $1, $1, $1 # $1 = 0 0020xa002 addi $0,$0,0x2 # $0 = 2 003 addi $1,$1,0x3 # $1 = 3 004 add $0,$0,$1 # $0 = 5 All numbers in hex

22. Fall 2006 22 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering

23. Fall 2006 23 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Basic questions Why do we have just two registers? Need only one bit to define What is the most positive and negative address offset? What is the range of the jump address? 0x000 to 0xfff = 0000 to 4095

24. Fall 2006 24 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Find machine instruction? InstructionTypeOp rsrtrdimmed /adr functMachine (hex) add $0, $0, $1 R0x1010na0x00x1400 andi $0, $1, 10f I0xc10na0x10fna0xa90f sll $0, $1 I0x210na 0x2400 lw $0, 323 ($1) I0x410na0x323na0x4b23 beq $0, $1, 17a I0x610na0x17ana0x657a j a64 J0x7na 0xa64na0x7a64

25. Fall 2006 25 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Assemble the simple program? AddressMachine Instruction Assembly Instruction Comment 0001001 sub $0, $0, $0 # $0 = 0 0011e01 sub $1, $1, $1 # $1 = 0 002a002 addi $0,$0,0x2 # $0 = 2 003ac03 addi $1,$1,0x3 # $1 = 3 0041400 add $0,$0,$1 # $0 = 5 All numbers in hex