1. DARE180U Platform Improvements in Release 5.6
Giancarlo Franciscatto

2. OUTLINE Introduction Design flow History Platform updates
Libraries and IP
Future work

3. DARE180U PLATFORM INTRODUCTION Radiation hardened ASIC design platform
Commercial UMC 0.18µm CMOS technology
Space and high-energy physics applications up to 1 Mrad
Supported by ESA
ITAR free components
“DARE library”  DARE180U platform
Libraries, IP and design services
Cost efficient -> commercial technology
Flexible -> users can build their own IP (ADK)
Known as “DARE180 library”
Not just libraries, but a design platform => combines libraries, IP and services

4. DARE180U PLATFORM DESIGN FLOW RTL Netlist DARE180U Libraries
Front-end design
DARE180U IP
Third-party IP
DARE180U Libraries
Optional service provided by imec IC-link
Back-end design
imec IC-link only  rad hard design verification
Fabrication
Assembly
Optional support services provided by imec IC-link
Synthesis can be done by imec or user/customer
Physical implementation done at imec to validate it for radhard
Test & Qualification

5. DARE180U PLATFORM HISTORY Release 5.6 (imec) 2002 2010 2011 2013 2017
2018
Release 1.0 (ESA)
CORE
I/O
SRAM
LVDS
PLL
DARE+ project (ESA)
Release 5.5
Release 5.6 (imec)
Release 4.1
First flight models
KNUT chip (TESAT)
TRL-9 status achievement
Hispasat36W-1 satellite launch
KNUT chip + antenna chip (Arquimea)
First publication in 2002
First flight model in 2010 by TESAT
Major review under ESA project DARE+ -> ended up with release 5.5
Flight mission qualification in 2017 with Hispasat launch -> TRL-9 status -> flight heritage

6. PLATFORM UPDATES
General updates common to all libraries

7. Platform Updates ADK CALIBRATED ELT model DARE180U ADK
ELT Pcell + simulation models + verification and extraction rules
Equivalent W/L CERN model
Good fit for drive strength
Underestimates gate capacitances (∝ W*L) for small transistors
Assumes symmetric drain/source overlap capacitances
Improvements in version 5.6
Validated equivalent W/L with test measurements
Accurate for NMOS
-5% deviation for PMOS with small B and H
Gate channel and overlap capacitances calculation based on inner/outer geometries
DARE180U uses ELT for high TID threshold
Test measurements done in DARE+ test chip

8. Platform Updates Analog-on-top design support
Aid customer IP design using DARE180U library building blocks
Full layout cell replacement and radiation/physical verification done by imec
Delivered views
OpenAccess symbols for schematic design
Encrypted netlists for simulation
Abstracts and netlists for black-box LVS

9. Libraries and IP

10. Libraries AND IP SUMMARY CORE library I/O library LVDS library
Bond pad library (new in 5.6)
SRAM compiler
Other IP (PLL, ADC, POR...)  later

11. Libraries AND IP CORE Library SEU hardened sequential cells
SET hardened cells for asynchronous and clock trees
Regular combinational cells for data paths
New in version 5.6
Optimized cell layouts for sensitive area
Added SET-hardened voter cell for TMR support (60 MeV.cm2/mg)
New timing characterization data
Calibrated ELT model  slower PMOS + higher gate capacitance
~ 10% delay degradation

12. Libraries AND IP CORE Library Layout optimization for sensitive area
More efficient ELT aspect ratio
Using outer diffusion nodes for less critical nodes
Chip Design
# Cells
Area v.5.5
Area v.5.6
Difference A
377769
mm2
mm2
-0.85% B
206548
mm2
mm2
-0.43% C
195267
mm2
mm2
-1.25%
Improved sensitive area while keeping same cell area

13. Libraries AND IP I/O AND LVDS Libraries 3.3V digital and analog I/O
Standard LVDS receiver and driver cells
Support to multi-domain I/O rings
New in version 5.6
Extended support to multi-domain I/O rings
New breaker cell types
Better support for analog and mixed-signal
New 1.8V analog I/O and supply cells  isolated 1.8V analog I/O domains
New 3.3V analog I/O cell variants
Improved reliability through better metallization
Mainly to extend support to multi-domain and mixed signal
For the first time, 1.8V analog I/O cells

14. Libraries AND IP BOND PAD LIBRARY
Previously distributed in I/O and LVDS libraries
New separate library in version 5.6
New bond pad opening size options
Added IP specific double bond pad cells
Reduced parasitic capacitance by 40%
Incorporated bond pads from I/O and LVDS cells

15. Libraries AND IP SRAM Compiler Single and dual port blocks
256 to 256K bits
Write-mask option
Bit interleaving 4, 8, 16, 32 or 64  MBU immunity
SEU insensitive possible with EDAC
New in version 5.6
Optimized top-level supply routing
Better decoupling and reliability
New timing characterization data with calibrated ELT model
Automated top-level supply routing for optimal rail count and decoupling

16. FUTURE WORK

17. Future WORK Version 5.7 1.8V digital I/O cells
Distributed Power-On Control
GPIO cells
LVDS cold-spare and failsafe

18. Questions? dare_support@imec.be
Hispasat36W-1 launch
Kourou, French Guyana
January 28th, 2017
Questions?