1. Development process of RHBD cell libraries for advanced SOCs
Ramon Chips
Ramon Chips is named in memory of Col. Ilan Ramon, Israeli astronaut who died on board the Columbia space shuttle, 1/2/2003
Development process of RHBD cell libraries for advanced SOCs
Tuvia Liran ]
Ran Ginosar ]
Dov Alon ]
Ramon-Chips Ltd., Israel

2. About Ramon Chips Private company Based in Haifa; Israel
Incorporated in 2004
Developed the RadSafeTM technology
Accomplished and delivered several space grade components to customers
Focused on advanced IC design for space

3. Dual core LEON3FT processor
Latest SOC products
JPIC -
JPEG2000 encoder
GR712RC -
Dual core LEON3FT processor

4. Outline Concepts of RadSafeTM technology RadSafeTM libraries
Design considerations
Development vehicles used
RadSafeTM 0.13µ technology

5. RadSafeTM concepts Radiation Hardening is achieved only by design
Same technology for all space applications
Based on standard CMOS technology
Radiation hardening guaranteed by similarity to previously qualified products/test chips
All IPs fully developed and owned by Ramon Chips
Proven immunity on Tower Semi 0.18µ technology
Complementary methodologies:
Design For Reliability
Flow for SEU/SET mitigation
Design for testability
Electrical screening
Class S screening flow

6. Radiation & Reliability effects mitigated by RadSafeTM
Radiation effects:
TID
SEL
SEU/SET in flip-flops
SEU in SRAMs
SEFI caused by PLL/DLLs
Reliability effects:
Electro-migration
Thermal cycling
Chemical effects
Mechanical (shock & vibration)

7. Mitigating TID effects
Advanced CMOS process – ≤0.18µ with STI
Fixed geometry of transistors – fixed geometry of parasitic devices; insensitive to placement
~30% area penalty – much less than ELT
TID immunity - >300Krad(Si)

8. Performance under TID stress
NMOS
PMOS
TID stress up to 250Krad(Si)

9. TID effect on ring oscillator frequency12
12.2
12.4
12.6
12.8 13
13.2
13.4 50
100
150
200
250
300
350
TID(krad)
freq. (MHz)
Dev #1
Dev #2
Dev #3
Dev #4
Dev #5
Ageing
Annealing
Before Irrad.
481 stages of inverters with FO = 4
Maximum variation in frequency is <0.5%

10. Mitigating SEU in flip-flops
Proprietary circuit
Optimized for area and power
LET threshold - ≥ 38MeV/cm2/mg
SET mitigation by glitch filtering of data
SET Filter for clock by several techniques
Restricting the use of async Set/Reset
All flip-flops on chip accessed by SCAN

11. Comparing FF alternatives
Area
Power
Tvalid
CLK->out
LET
Threshold
MeV*cm2/mg
Errors/bit/day
Un-protected 1
2.94
5E-7
TMR
4.01
2.6
2.5 -
DMR
2.48
2.2
DMR+
2.34
2.1
38.2
4E-14
SEP
1.8
1.6
1.2
4E-12
SER (**)
1.75
1.5
Relative values
Refers to standard FF, with scan, same output drive
(*) Refers to 37o inclination, quite solar
(**) Designed for 0.13u only

12. I/O cell libraries Two libraries: Special rad-hard ESD cells
For 1.8V core voltage
For 3.3V core voltage
Special rad-hard ESD cells
Special cells:
LVDS (>400MHz)
SSTL, HSTL, AGP
5V tolerance
Cold spare
Proven on several chips

13. Special design rules for I/O cells
RH mitigation:
≥2 guard rings
All NMOS transistors ringed by P+/GND
Special ESD considerations
Other considerations for space ICs:
Large pitch/size pads – enables thick Al bond wires
Relaxed layout rules – reduced thermo-mechanical stress
Dual slope transition – reduced ringing
Double supply pads – reduced inductance & density

14. RadSafe SRAM cell Conventional SRAM cell RadSafeTM SRAM cell
Many NMOS devices connected to bit-lines
Conventional SRAM cell
Only PMOS devices connected to bit-lines
RadSafeTM SRAM cell

15. Examples of SRAM cores

16. SRAM cell libraries Variable sizes, up to 2Kx40
Two types of SRAM cores:
Single / dual port (>250MHz / >120MHz)
Two operation voltages: 1.8V, 3.3V
DPRAM performs read & write access per cycle
Integrated EDAC & BIST in each core
Very low power; zero standby power
Protected from all radiation effects:
MBU is eliminated
LET threshold 3 MeV·cm2/mg (before EDAC correction)
In tests, all errors corrected by EDAC
Testability features:
Complementary BIST logic
Speed control
Weak write
Iddq compatibility

17. All-digital DLL cores Three DLL cores for 3 frequency ranges
Locking guaranteed & fast
Immediate re-locking
0.05 mm2/core 8
Highly protected from radiation effects
Can be placed anywhere in the core
Powered by core supply lines

18. Technology development chips
RADIC2
1.8/3.3V transistors
1.8/3.3V std. cells
1.8/3.3V ring oscillators
1.8/3.3V shift registers
4Kbit SRAM
ADDLL
FPGA converted chip
RADIC3
1.8V transistors
1.8V std. cells
1.8V ring oscillators
1.8V shift registers
Several FF types
256Kbit DPRAM
ADDLL
LVDS I/O buffers
GR702RC
LEON3FT core by GR
Fully automatic flow
2 SpW ports w LVDS
2 ADDLL
10 SRAM cores

19. RadSafe™ 0.13µ technology Density: Power - <40% of 0.18µ
Logic - >120Kgates/mm (40K at 0.18m)
SRAMs - >200Kbit/mm2 (80K at 0.18m)
Power - <40% of 0.18µ
Speed - >200MHz [for large chips]
Special IPs:
10 bit, 1Msps, 1mW SAR ADC
Status:
Test chip ready for production

20. RADIC4 – Test chip for RadSafe_013 technology
3 shift registers
3 delay lines/
SET monitor
10b RH ADC
(1Msps,1mW)
NMOS/PMOS
Xtors
4Kx72 RH SRAM
4Kx72 RH SRAM
With process
enhancement

21. 10b Analog to Digital Converter
Resolution: 10 bit
Sampling rate: 0.5Msps
Power: <1.5mW
Area: ~0.03mm2
TID: >300Krad (target)
Process: 0.13µ
Voltage: 3.3/1.2V

22. Summary RadSafe™ by Ramon Chips Using standard process
Using standard EDA tools & flow
Proven Rad-Hard-by-design on several chips
Optimized for performance, power & reliability
RH considerations applies to all levels of design flow
0.13µ process provides significant performance advantages