1. Programmable Logic Devices
Lecture No. 20
Programmable Logic Devices
Asalam O Aleikum students. I am Waseem Ikram.
This is the twentieth lecture in a series of 45 lectures on Digital Logic Design.

2. Recap Demultiplexer PLDs PLD types ALU to Register Series to Parallel
PROM
PLA
PAL
GAL
3 minute

3. Recap PAL PLA Programming Simplified representation
Programmable outputs
PAL ID
PLA
Circuit
3 minute
6 minutes

4. PLA Implementing Constant 0s and 1s (fig 1)
Implementing Odd-Prime Number (fig 2)
4 minutes
10 minutes

5. GALs Generic Array Logic structure (fig 3, 4)
Output Logic Macro Cells OLMCs (fig 5)
GAL ID (fig 6)
Programming of GAL
Boolean expression, truth table, state diagram
Test vector verification
Documentation and fuse map
8 minutes
18 minutes

6. GAL22V10 Circuit diagram (fig 7) 12 inputs 10 outputs 10 OLMCs
Different number of inputs to OLMCs, 8,10,12,14,16
GAL different versions 3.3 v and In-System
4 minutes
22 minutes

7. GAL22V10 OLMCs Circuit diagram of OLMCs(fig 8)
Combinational mode with active-low (fig 8)
Combinational mode with active-high (fig 8)
Registered mode with active-low
Registered mode with active-high
Tri-state Buffers (fig 9)
Detailed connection (fig 10)
Programming Boolean Expression (fig 11)
10 minutes
32 minutes