1. Boolean Algebra and Logic Simplification
Chapter 4
Boolean Algebra and Logic Simplification

2. Boolean Operations and Expressions
Boolean Addition (OR)

4. Boolean Multiplication (AND)

6. Laws and Rules of Boolean Algebra
Commutative
Associative
Distributive
Rules

7. Figure 4--1 Application of commutative law of addition.

8. Figure 4--2 Application of commutative law of multiplication.

9. Figure 4--3 Application of associative law of addition

10. Figure 4--4 Application of associative law of multiplication

11. Figure 4--5 Application of distributive law

12. Rules of Boolean Algebra

13. Figure RULE 1

14. Figure RULE 2

15. Figure RULE 3

16. Figure RULE 4

17. Figure RULE 5

18. Figure RULE 6

19. Figure RULE 7

20. Figure RULE 8

21. Figure RULE 9

25. DeMorgan’s Theorem
Figure Gate equivalencies and the corresponding truth tables that illustrate DeMorgan’s theorems. Notice the equality of the two output columns in each table. This shows that the equivalent gates perform the same logic function.

28. Boolean Expression for a Logic Circuit
Figure A logic circuit showing the development of the Boolean expression for the output.

29. Constructing a Truth Table for a Logic Circuit
Evaluating the expression and putting results in truth table format

30. Simplification Using Boolean Algebra

31. Figure 4--17 Gate circuits for Example 4-8

32. Standard Forms of Boolean Expressions
Sum-of-Products (SOP) Form
Product-of-Sum (POS) Form

33. Figure 4--18 Implementation of the SOP expression AB + BCD + AC.
SOP Form
Figure Implementation of the SOP expression AB + BCD + AC.

35. Standard SOP Form

36. Binary Representation of Product Term

38. POS Form
Figure Implementation of the POS expression (A + B)(B + C + D) (A + C).

39. Standard POS Form

40. Binary Representation of Sum Term

41. Converting Standard SOP to Standard POS

42. Converting SOP to Truth Table

43. Converting POS to Truth Table

44. Determining Standard Expressions from Truth Table

46. Figure 4--20 A 3-variable Karnaugh map showing product terms.

47. Figure 4--21 A 4-variable Karnaugh map.

48. Figure Adjacent cells on a Karnaugh map are those that differ by only one variable. Arrows point between adjacent cells.

49. Figure 4--23 Example of mapping a standard SOP expression.
Karnaugh Map SOP Minimization
Figure Example of mapping a standard SOP expression.

50. Figure 4--24

51. Figure 4--25

52. Mapping Nonstandard SOP Expression

53. Figure 4--26

55. Figure 4--27

56. Karnough Map Simplification of SOP Expressions
Example Group the 1s in each Karnaugh maps

57. Figure 4--29

58. Figure Determine SOP
Related Problem: add 1 in the lower right cell (1010) and determine the resulting SOP.

59. Figure 4--31
Related Problem: For the Karnaugh map in Fig. 4-31(d), add 1 in the 0111 cell and determine the resulting SOP.

62. Mapping Directly from Truth Table
Figure Example of mapping directly from a truth table to a Karnaugh map.

63. “Don’t Care” Conditions
Figure Example of the use of “don’t care” conditions to simplify an expression.

64. Karnaugh Map POS Minimization
Figure Example of mapping a standard POS expression.

65. Example 4-30

66. Figure 4--38

69. Figure 4--39

70. Converting b/w POS and SOP Using Karnaugh Map

71. Five-Variable Karnaugh Maps
Figure A 5-variable Karnaugh map.

72. Figure 4--42 Illustration of groupings of 1s in adjacent cells of a 5-variable map.

73. Figure 4--43

74. Figure 4--44 Basic structure of a PAL.
Programmable Logic
Figure Basic structure of a PAL.

75. Figure 4--45 PAL implementation of a sum-of-products expression.

76. Digital System Application
Figure Seven-segment display format showing arrangement of segments.

77. Figure 4--52 Display of decimal digits with a 7-segment device.

78. Figure 4--53 Arrangements of 7-segment LED displays.

79. Figure 4--55 Block diagram of 7-segment logic and display.

80. Figure 4--56 Karnaugh map minimization of the segment-a logic expression.

81. Figure 4--57 The minimum logic implementation for segment a of the 7-segment display.