1. Digital Logic & Design Dr.Waseem Ikram Lecture No. 43

2. Recap FLASH Structure Common Drain lines Common Source lines (column select lines) Row select activates all cells Current flows through common drain line to active load Voltage drop across active load compared with reference voltage High output indicates 0 stored and vice versa

3. Recap FIFO Memory Connecting two devices communicating at different data rates Direct connection Connection through buffer Buffer contents writing/reading Keyboard buffer FIFO Implementation using shift registers FIFO Implementation using Memory

4. A five byte LIFO Memory

5. Memory Based Stack

6. 1 MByte Memory Map 00000H 10000H 20000H 30000H 40000H 50000H 60000H 70000H 80000H 90000H A0000H B0000H C0000H D0000H E0000H F0000H 1 M byte Memory Space Base Address ROM Data RAM Program RAM Stack RAM Vacant

7. Implementing 4K Word RAM using two 4K Byte RAM chips

8. Implementing 8K Byte RAM using two 4K Byte RAM chips

9. An 8K x 16 RAM implemented using four 4K x 8 memory chips

10. Address Decoding of three 4KByte memory chips

11. Memory Map for the three 4K RAM chips A 13 A 12 Output 00CS0 01CS1 10CS2 11CS3 4K RAM0 4K RAM1 4K RAM2 Vacant

12. Logic Gate based Address Decoder

13. 2 x 4 and 3 x 8 Decoder based Address Decoders

14. Block diagram of a FPA

17. LIFO Memory Use of Stack in Computer systems Implementing LIFO using parallel In and parallel out shift registers (fig 1) Implementing Stack using Memory (fig 2)

18. Memory Expansion Memory Requirement is large Memory Implemented small Standard data unit size Standard number of memory locations Base address of memory Memory Map fig (3) 1 MB memory map Divided into 16, 64K blocks ROM, Data, Program, Stack 12, 64K vacant blocks for expansion

19. Memory Expansion Expanding Data Unit size (fig 4) Expanding Locations (fig 5) Expanding Data unit size and locations (fig 6) Address Decoders Accessing memory at specified base address (fig 7) Logic gate decoders (fig 8) n x m gate decoders (fig 9)

20. FPGAs Field Programmable Logic Array (fig 10) Logic blocks Generate logic functions by programming LUT Row & Col programmable interconnects I/O programmable blocks