1. Morgan Kaufmann Publishers The Processor
6 December, 2018
Chapter 4
The Processor
Chapter 4 — The Processor

2. Morgan Kaufmann Publishers
6 December, 2018
Introduction
§4.1 Introduction
CPU performance factors
Instruction count
Determined by ISA and compiler
CPI and Cycle time
Determined by CPU hardware
We will examine two MIPS implementations
A simplified version
A more realistic pipelined version
Simple subset, shows most aspects
Memory reference: lw, sw
Arithmetic/logical: add, sub, and, or, slt
Control transfer: beq, j
Chapter 4 — The Processor — 2
Chapter 4 — The Processor

3. Morgan Kaufmann Publishers
6 December, 2018
The MIPS Processor
§4.1 Introduction
MIPS was an instruction set that was introduced in 1981 by MIPS Technologies.
It’s a Reduced Instruction Set Computing or RISC design. The goal was to have many small fast and simple instructions
A popular processor to study and used in many devices. The instruction set is a part of current processors like the powerpc.
Some devices that used it were the Playstation, Playstation 2, Playstation Portable, Various Routers and many other embedded devices.
Chapter 4 — The Processor — 3
Chapter 4 — The Processor

4. Instruction Execution
Morgan Kaufmann Publishers
6 December, 2018
Instruction Execution
PC  instruction memory, fetch instruction
Register numbers  register file, read registers
Depending on instruction class
Use ALU to calculate
Arithmetic result
Memory address for load/store
Branch target address
Access data memory for load/store
PC  target address or PC + 4
Simply put this is known as Fetch, Decode, Execute…
Chapter 4 — The Processor — 4
Chapter 4 — The Processor

5. Morgan Kaufmann Publishers
6 December, 2018
CPU Overview
Chapter 4 — The Processor — 5
Chapter 4 — The Processor

6. Morgan Kaufmann Publishers
6 December, 2018
MIPS Register file
MIPS register file
32 registers, 32-bits each
Write port indexed via RW
Writes occur on falling edge but only if WE is high
Read ports indexed via RA, RB
Dual-Read-Port Single-Write-Port
32 x 32 Register File
DataW
DataA 32 32
DataB 32 WE RW RA RB 1 5 5 5
Chapter 4 — The Processor — 6
Chapter 4 — The Processor

7. MIPS ALU Arithmetic Logic Unit
Morgan Kaufmann Publishers
6 December, 2018
MIPS ALU Arithmetic Logic Unit
MIPS ALU
Two 32-bit inputs
One 32-bit output
Zero is a logic level high when ALUOut = 0
An ALU is a combinational circuits
ALUctl
ALU Operation
ALU Output
0000
AND
A & B
0001 OR
A | B
0010
ADD
A + B
0110
SUBTRACT
A - B
0111
SET ON LESS THAN
1 if A < B
Chapter 4 — The Processor — 7
Chapter 4 — The Processor

8. Morgan Kaufmann Publishers
6 December, 2018
Multiplexers
Can’t just join wires together
Use multiplexers
Chapter 4 — The Processor — 8
Chapter 4 — The Processor

9. Morgan Kaufmann Publishers
6 December, 2018
Control
Chapter 4 — The Processor — 9
Chapter 4 — The Processor

10. Morgan Kaufmann Publishers
6 December, 2018
Building a Datapath
Datapath
Elements that process data and addresses in the CPU
Registers, ALUs, mux’s, memories, …
We will build a MIPS datapath incrementally
Refining the overview design
§4.3 Building a Datapath
Chapter 4 — The Processor — 10
Chapter 4 — The Processor

11. Morgan Kaufmann Publishers
6 December, 2018
Instruction Fetch
Increment by 4 for next instruction
32-bit register
Chapter 4 — The Processor — 11
Chapter 4 — The Processor

12. R-Format Instructions
Morgan Kaufmann Publishers
6 December, 2018
R-Format Instructions
Read two register operands
Perform arithmetic/logical operation
Write register result 32 32 32 32 32 32
Chapter 4 — The Processor — 12
Chapter 4 — The Processor