1. ASIC = “Application specific integrated circuit”

2. CS 2630 Computer Organization
Meeting 19: Building a MIPS processor
Brandon Myers
University of Iowa

3. The goal: implement most of MIPS
This system is what we are going to get to. We have all the tools from comb and seq logic to build it.
Now we just need to understand how to put the pieces together.
The way we are going to get to this picture, is by implementing the simplest processor possible (will only understand the addu instruction)
and then incrementally adding support for more instructions.

4. So far
PM fa16: Need to show without enable bit

5. Implementing the addu instruction
register file

6. support more than 1 kind of arithmetic operation
PM fa16: Need to show without enable bit
still need to:
support more than 1 kind of arithmetic operation
feed the CPU with a program
support branches and load/store

7. Next: we’ve discussed what is in this box, but we need to learn about the rest of what is needed for a MIPS processor
Project 2-1: the stuff in this box
Project 2-2: everything else

8. Implementing the addu instruction
register file
How do we program the “addu machine”?

9. Peer instruction
Give the sequence of addu machine inputs to perform $t0 = $t1 + $t2 + $t3
1st clock cycle: rd=8, rs=9, rt=10 2nd clock cycle: rd=8, rs=8, rt=11
1st clock cycle: rd=0, rs=9, rt=10 2nd clock cycle: rd=8, rs=0, rt=0 3rd clock cycle: rd=0, rs=8, rt=11 4th clock cycle: rd=8, rs=0, rt=0
1st clock cycle: rd=0, rs=10, rt=11 2nd clock cycle: rd=8, rs=0, rt=0 3rd clock cycle: rd=0, rs=8, rt=9 4th clock cycle: rd=8, rs=0, rt=0
1st clock cycle: rd=9, rs=10, rt=11 2nd clock cycle: rd=8, rs=0, rt=0

10. How do we program the addu machine?
Example: 8 8 14
On each clock cycle, we are allowed to change the inputs rd, rs, and rt to perform another addition.

11. But, where do those inputs come from?

13. mining difficulty year
write on the board the following outline
How do we add control instructions?
How do we add load and store?
How do we build the control unit?
BTC a digital currency and people are building custom chips to mine for it.
BTC miners: there is a single list of transactions (called block chain) and if you do the work to be the one to add a new transaction to the chain first, you get on the order of 12 bitcoin which is about $7000 USD at the moment.
“the difficulty target is adjusted based on the network's recent performance, with the aim of keeping the average time between new blocks at ten minutes. In this way the system automatically adapts to the total amount of mining power on the network” wikipedia.org/wiki/Bitcoin citing Andreas M. Antonopoulos (April 2014). Mastering Bitcoin. Unlocking Digital Crypto-Currencies. O'Reilly Media. ISBN 

14. CS 2630 Computer Organization
Meeting 20: Building a MIPS processor
Brandon Myers
University of Iowa

15. But, where do those inputs come from?
the instruction memory
PM sp17:
in 50minutes I quickly discussed the answers to building_memories_from_memories and I got through this slideshow to this slide. Good ending point because it gives them a sense of where we are headed.
recall the layout of bits in R-type instructions

16. How do we know which instruction we are on?

17. How do we know which instruction we are on?
Store the current address in a 32-bit register called the program counter (PC)
Add 4 each cycle to go to the next word (next instruction)

18. The complete addu machine

19. Architecture and microarchitecture
also known as ISA, the programmer’s interface
it includes the things on the MIPS reference sheet: 32 registers, PC, instructions and their behavior (RTL)
an implementation of the ISA
we’ll examine at least two kinds of microarchitectures for MIPS
right now: a single-cycle design where an instruction executes in one clock period
later: a pipelined design where an instruction takes multiple clock periods

20. The complete addu machine
But, how do we get data into the addu machine? All registers start with
the value 0.
Let’s modify the circuit to include addiu

21. Peer instruction
Modify the processor so it also knows how to execute both addiu and addu
Hint 2: get the immediate out of the instruction data and do something with it
Assume you have a component called “control” that takes a MIPS opcode as input
and provides a 1-bit signal isAddiu as output.
isAddiu = 0 if the opcode is 0x0 (the opcode for addu)
isAddiu = 1 if the opcode is 0x9 (the opcode for addiu)
control
opcode
isAddiu
bonus: implement
the inside of “control”

22. Addu/addiu machine
Look at RTL of addu and addiu. What are the differences?
Where do we get the immediate from?
Each difference in the RTL can be handled with a MUX
Interesting points: there was a 2-cycle solution, too
lookup “microcode” for more information about that kind of design

23. Project 2: MIPS processor
Project 2-1 is assigned
one submission per team
Project 2-1: ALU and register file and tests
Project 2-2: datapath and control path of pipelined MIPS processor, tests, and test programs

24. Project 2-1: ALU ALU stands for arithmetic logic unit
define the ALU
Notice that the output Equal is different from the Zero? signal from the textbook and lecture examples

25. Project 2-1: ALU
Switch plays the same role as the signal ALU control in the textbook. However, mind the
differences!
Do not bother building your own adder/shifter/comparator! You can use any built-in Logisim component.

26. Project 2-1: testing the ALU
You must use a Linux environment to run the tests.
Many options for students using Windows computers:
connect to instructional machines through ssh (using WinSCP) or through fastx.divms.uiowa.edu
Use the lab machines directly
Use a Virtual machine
Use cygwin
if Windows 10, then enable Ubuntu console
For students using Linux or MacOSX computers:
use the terminal
Ask for help early! There is no excuse to not run the tests.

27. Project 2-1: The register file
An addressable memory with 2 read ports and 1 write port!
$0 must always hold 0
Inputs
Read Register 1 5
The number of the register whose contents is read out to Read Data 1
Read Register 2
The number of the register whose contents is read out to Read Data 2
Write Register
The number for the register to be written at the rising edge of Clock
Write Data 32
The data to write to the register specified by Write Register
Write Enable 1
If 1, then a register will be written at the rising edge of Clock. If 0, no register will be written at the rising edge of Clock.
Clock
The clock signal
The “Debugging outputs” provide access to some of the internal state of the register file
Outputs
Name
Bit width
Description
Read Data 1 32
The data read from the register specified by Read Register 1
Read Data 2
The data read from the register specified by Read Register 2
$s0 Value
(Debugging output) the value stored in register $s0)
$s1 Value
(Debugging output) the value stored in register $s1)
$s2 Value
(Debugging output) the value stored in register $s2)
$ra Value
(Debugging output) the value stored in register $ra)
$sp Value
(Debugging output) the value stored in register $sp)

28. Project 2-1 If you cannot decide on a split of the work, you can try
1 person in charge of ALU
1 person in charge of register file
1 person in charge of creating tests
This is just a way to organize the work; every team member is responsible for ensuring the team completes the whole project.

29. SO FAR
NEXT

30. Next steps Add more instructions to our processor:
other R and I types (or, ori, subu)
load and store (lw, sw)
branches (beq/bne)
jumps (j, jr, jal)
How do we implement the control logic?

31. Addu/addiu machine
sign extend

32. Using memory for data Load word Store word
Draw the “Data Memory” on the right side of your processor
Using the RTL above, add circuitry that is sufficient for executing load word (lw).
Assume that you have a 1-bit control signal isLW (1 when instruction is a lw, 0 otherwise)
Using the RTL above, add circuitry that is sufficient for executing load word (sw). If you need a control signal, just pick a descriptive name.
Assume that you have a 1-bit control signal isSW (1 when instruction is a sw, 0 otherwise)

33. Branch instructions beq
PC behavior for non branch/jump instructions
PC <- PC + 4
beq
Add new circuitry or identify existing circuitry used to implement the comparison R[$rs]=R[$rt]
Add circuitry to implement SignExt18b({imm,00}).
Notice the difference in what happens to the PC register.
Add circuitry to choose between what the next PC is.
Add a new control signal Branch=1 when instruction is a branch instruction, 0 otherwise.
Did you add a MUX? Add necessary logic to calculate its Select input.
RTL from

35. How to control the ALU’s operation
ALUControlUnit
opcode
switch (aka, ALUControl)
Switch
funct
Note that the textbook has a slightly different design where the “main decoder” produces a signal, ALUOp, that tells the ALUDecoder some information based on only the Opcode
DDCA, 2nd Ed

36. When you just “don’t care”
A “don’t care” is where you put an X in the truth table to indicate that it doesn’t matter if the bit is a 0 or a 1.
X’s can drastically simplify the truth table and the resulting combinational logic circuit. Why? The person/tool simplifying the circuit can pick whether a 1 or 0 for the X makes the circuit simpler.
Example from your recent experience...
“What should happen to the Soda Machine FSM when Dime and Nickel inputs are both 1 in the same clock period?”
If our circuit’s behavior is unspecified for a certain input case then we can put X’s into the truth table.
You can also put X’s in the output column
an X in the output means that you don’t care what the output is for a certain input case
if you use Logisim’s logic analyzer, be aware that it allows for X’s in the output bits but not the input bits
Do not confuse “don’t cares” (X’s in the truth table) with Logisim’s RED wires (i.e., wires where the value has X’s in it). Red wires are always bad.

37. Logic analyzer in Logisim
Let’s automatically generate the gates for a truth table A B Z 1 x
Create Pins for A,B,Z (limitation: must be 1 bit)
Project | Analyze circuit
In Table tab, enter your truth table values
Click Build Circuit
Can click through default options. You get an implementation!
can include “don’t cares” in the output

38. Control unit truth table
Instruction
Opcode
Regwrite
RegDst
ALUSrc
Branch
MemWrite
MemToReg
ALU operation
R-type
000000 1
depends
addiu
add lw sw
beq
Have the students fill in this table; need to display the processor, too so they have the same names
---
PM fa16
Ended at the point where students were able to fill out some of the cells but certainly not finish

39. Control unit truth table
Instruction
Opcode
Regwrite
RegDst
ALUSrc
Branch
MemWrite
MemToReg
ALU operation
R-type
000000 1
depends
addiu
add lw sw
beq
Have the students fill in this table; need to display the processor, too so they have the same names
---
PM fa16
Ended at the point where students were able to fill out some of the cells but certainly not finish