1. COSC 2021: Computer Organization Instructor: Dr. Amir Asif
Department of Computer Science
York University
Handout # 7 Designing a MIPS Processor I: Datapath
Topics:
1. Basics: Clock, Latches and Flip Flops
2. Sequential and Combinational Circuits
3. Building a Datapath
Patterson: Appendices C.7 and Sections 4.1 – 4.4

2. Review: Arithmetic Logic Unit
Previously we designed an ALU using a Combinational circuit.
The 32-bit ALU performs the data transfer, arithmetic, logical, and branch operations
To complete the design of processor, we will show how ALU is connected to the main
memory using datapath and control lines.
ALU Control Lines
Result
Binvert
Carry In
Operation
0 = (00)two
AND (a·b)
1 = (01)two
OR (a+b)
2 = (10)two
Add sum(a,b) 1
Subtract (a - b)
3 = (11)two
SLT if (a < b) Result0 = 1
Test Equality Zero = 1 if (a < b) A L U R e s u l t Z r o O v f w a b p i n C y 3 1
MIPS 32-bit ALU

3. Arithmetic and Logical
Overview (1)
Goal: Implement a subset of core instructions from the MIPS instruction set, given below
Category
Instruction
Example
Meaning
Comments
Arithmetic and Logical
add
add $s1,$s2,$s3
$s1 ← $s2+$s3
subtract
sub $s1,$s2,$s3
$s1 ← $s2-$s3
and
$s1 ← $s2&$s3
& => and or
or $s1,$s2,$s3
$s1 ← $s2|$s3
| => or
slt
slt $s1,$s2,$s3
If $s1 < $s3, $s1←1 else $s1←0
Data Transfer
load word
lw $s1,100($s2)
$s1 ← Mem[$s2+100]
store word
sw $s1,100($s2)
Mem[$s2+100] ← $s1
Branch
branch on equal
beq $s1,$s2,L
if($s1==$s2) go to L
unconditional jump
j 2500
go to 10000

4. Overview (2) For each instruction, the first two steps are the same
Step 1: Based on the address in the program counter (PC), fetch instruction from memory
Step 2: Read 1 or 2 registers specified in the instruction
Steps 3 and 4 vary from one instruction to another
Step 3: Perform the arithmetic operation specified by the instruction
load/store word (sw/lw): add offset to $s2
(add/sub/and/or): appropriate operation is performed on $s2, $s3
(beq/slt): compare $s2 and $s3 (requires $s2 - $s3)
jump (j): calculate address
Step 4: Complete the instruction
sw: write data into memory
lw: read data from memory
add/sub/and/or: store result in $s1
beq/j: jump to the appropriate instruction
In this lecture, we will focus on the hardware implementation of each of these instructions

5. Abstract view of the Implementationg i s t r # D a m o y A d P C I n u c L U
Program counter provides the instruction address
Instruction is fetched from instruction memory based on address in the PC
Register numbers are specified by the instruction
ALU computes an arithmetic result or address of memory
Arithmetic operation: Result is saved in a register
Data transfer: Data is extracted from data memory & transferred to a register or vice versa

6. Basics: Sequential vs. Combinational Circuits (1)
Digital circuits can be classified into two categories
Combinational Circuits:
Output depends only on the current input
Same set of inputs will always produce the same output
Consist of AND, OR, NOR, NAND, and NOT gates
Common examples are adder circuits and ALU
Sequential Circuits:
Output depends on the current input and state of the circuit
Same set of inputs can produce completely different outputs
Consist of memory elements such as flip-flops and registers in addition to combinational circuits
Examples are traffic signals and street lights
Datapath and control circuits of an ALU use sequential circuits.

7. Basics: Clocks (2)
Clock is a periodic signal oscillating between low and high states with fixed cycle time.
Clock frequency is inverse of clock cycle time. What is the cycle time for 1GHz clock?
Clock controls when the state of a memory element changes.
We assume falling edge-triggered clocking implying that the state changes only at the falling edge. When is the state element 2 modified in the following circuit? C l o c k p e r i d R s n g F a C l o c k y e S t a m n 1 b i g 2

8. Basics: RS Latch (3) RS Unclocked Latch
Simplest memory elements are Flip-flops and Latches
In clocked latches, state changes whenever input changes and the clock is asserted.
In flip-flops, state changes only at the trailing edge of the clock
For a RS-latch: output Q = 1 when S = 1, R = 0 (set condition)
output Q = 0 when S = 0, R = 1 (reset condition)
Inputs
Outputs
Comments S R Q 1
Initial Condition
After S = 1, R = 0
After S = 0, R = 1
Undefined Q _ R S _ Q
Logic Diagram
Function Table
RS Unclocked Latch

9. Basics: Clocked D Latch (4)
For a D-latch: output Q = 1 when D = 1 (set condition)
output Q = 0 when D = 0 (reset condition)
2. D Latch requires clock to be asserted for output to change Q C D _ R
Inputs
Outputs
Comments _ C D Q Q X
Unchanged 1 1
Reset S 1 1 1
Set
Logic Diagram
Function Table D C Q
Setup Time
Hold
Time

10. Basics: 32-bit Registers (6)
Falling edge triggered D flip-flops can be combined to form a register
32-bit Register Q D C
flipflop A0 S0 A1 S1 A2 S2
A31
S31
Clock

11. Basics: Register Files (6)
Register files consist of a set of registers that can be read or written individually
In MIPS, register file contains 32 registers
Two registers can be read simultaneously
One register can be written at one time R e a d r g i s t n u m b 1 2 f l W

12. Basics: Read Operation in Register Files (7)
Register number of the register to be read is provided as input
Content of the read register is the output of the register file
Multiplexers are used in the read operation M u x R e g i s t r 1 n – a d 2
# 1
# 2
Register File 5 5

13. Basics: Write Operation in Register Files (8)
Register number of the register to be written is one input
Data to be written is the second input
Clock that controls the write operation is the third input
Decoders are used in the write operation
Inputs
Outputs
In2
In1
In0
Out7
Out6
Out5
Out4
Out3
Out2
Out1
Out0 1
What is a Decoder? O u t 1 2 3 4 5 6 7 D e c o d r
3-bit Decoder

14. Basics: Write Operation in Register Files (9)
Register number of the register to be written is one input
Data to be written is the second input
Clock that controls the write operation is the third input
Decoders are used in the write operation n - t o 1 d e c r R g i s – C D u m b W a
Register File

15. Basic Building Blocks (1)6 3 2 S i g n e x t d . - s o u t:
extends a 16-bit integer to a 32-bit integer P C 1 . r o g a m c u n t e r:
contains address of next instruction 4 . A L U: U c o n t r l e s u Z 3
add/subtract/and/or/compare two 32-bit integers A d S u m 3 . e r:
adds two 32-bit integers

16. Basic Building Blocks (2)t r u c i o M e m y a d 5 . 6 . D a t m e o r y u n i M R d W A s R n 7 . e g i s t r
Files W Re a d 1 2 D u m b 5

17. Datapath: Fetch Instruction
Provide address from PC to Instruction Memory
Increment PC by 1 word (4 bytes)
Fetch the instruction P C I n s t r u c i o m e y R a d 4 A

18. Datapath: R-type Instructions
R-type instructions include arithmetic and logical instructions (add, sub, or, and, slt)
Example: add $s1,$s2,$s3
1. Read two registers ($s2,$s3) specified in the instruction
2. ALU performs the required operation (add) on the two operands
3. Output of ALU is written to the specified register ($s1) I n s t r u c i o R e g W a d 1 2 A L U l Z p 3

19. Datapath: Data transfer Instruction (1)
Store instruction sw $s1,offset($s2)
1. Read two registers ($s1,$s2) specified in the instruction.
2. Offset is extended to 32 bits.
3. ALU adds offset with specified register ($s2) to obtain data memory address.
4. Address along with data of the register ($s1) to be stored passed to data memory. A L U o p e r a t i o n R e a d 3 r e g i s t e r 1 M e m W r i t e R e a d d a t a 1 R e a d I n s t r u c t i o n r e g i s t e r 2 Z e r o R e g i s t e r s A L U A L U W r i t e R e a d r e s u l t A d d r e s s r e g i s t e r d a t a R e a d d a t a 2 W r i t e D a t a d a t a m e m o r y W r i t e d a t a 1 6 3 2 S i g n e x t e n d

20. Datapath: Data transfer Instruction (2)
Load instruction lw $s1,offset($s2)
1. Read register ($s2) specified in the instruction Offset is extended to 32 bits.
3. ALU adds offset with specified register ($s2) to obtain data memory address.
4. Data memory transfers data from provided address to Register file where it is stored in the specified register ($s1). A L U o p e r a t i o n R e a d 3 r e g i s t e r 1 R e a d d a t a 1 R e a d I n s t r u c t i o n r e g i s t e r 2 Z e r o R e g i s t e r s A L U A L U W r i t e R e a d r e s u l t A d d r e s s r e g i s t e r d a t a R e a d d a t a 2 W r i t e D a t a d a t a m e m o r y W r i t e R e g W r i t e d a t a 1 6 3 2 S i g n M e m R e a d e x t e n d

21. Datapath: Data transfer Instruction (3)
Load and store instruction combined I n s t r u c i o 1 6 3 2 R e g W a d D m y S x A L U l Z M p
for store only
for load only

22. Datapath: Branch Instructions1 6 3 2 S i g n e x t d Z r o A L U u m h f l T b a c B P C + 4 s p I R W
Example: beq $s1,$s2,Loop
Compiler translation:
beq $s1,$s2,w_offset #if $s1==$s2, goto (PC+4+4*w_offset)
1. Read two registers
($s2,$s3) specified
in the instruction
2. ALU compares
content of specified
registers ($s1,$s2)
3. Adder computes
the branch address
4. If equal (zero = 1),
branch address is
copied to PC

23. Combined Datapath P C I n s t r u c i o m e y R a d 1 6 3 2 A L U l Mx g W S h f 4 p Z D

24. Combined Datapath: Arithmetic Operations (add,sub,or,and,slt)
add/sub/or/and/slt $s1,$s2,$s3 P C I n s t r u c i o m e y R a d 1 6 3 2 A L U l M x g W S h f 4 p Z D

25. Combined Datapath: Data Transfer (load)
lw $s1, offset($s2) P C I n s t r u c i o m e y R a d 1 6 3 2 A L U l M x g W S h f 4 p Z D

26. Review: Data Transfer (store)
sw $s1, offset($s2) P C S r c M A d u x 4 A d d A L U r e s u l t S h i f t l e f t 2 R e g i s t e r s A L U o p e r a t i o n R e a d 3 M e m W r i t e R e a d r e g i s t e r 1 A L U S r c P C R e a d a d d r e s s R e a d d a t a 1 M e m t o R e g r e g i s t e r 2 Z e r o I n s t r u c t i o n A L U A L U W r i t e R e a d R e a d A d d r e s s r e g i s t e r d a t a 2 M r e s u l t d a t a M I n s t r u c i o m e y u u W r i t e x D a t a x d a t a m e m o r y W r i t e R e g W r i t e d a t a 1 6 3 2 S i g n e x t d M e m R a d

27. Review: Data Transfer (branch)
beq $s1, $s2, w_offset P C I n s t r u c i o m e y R a d 1 6 3 2 A L U l M x g W S h f 4 p Z D