1. COMP541 Datapaths I
Montek Singh
Mar 28, 2012

2. Topics Over next 2 classes: datapaths
How ALUs are designed
How data is stored in a register file
Lab 9: Start building a datapath!

3. What is computer architecture?

4. Architecture (ISA) Jumping up a few levels of abstraction.
Architecture: the programmer’s view of the computer
Defined by instructions (operations) and operand locations
Microarchitecture: how to implement an architecture in hardware

5. MIPS Machine Language Three instruction formats:
R-Type: register operands
I-Type: immediate operand
J-Type: for jumps

6. R-Type instructions Register-type 3 register operands: Other fields:
rs, rt: source registers
rd: destination register
Other fields:
op: the operation code or opcode (0 for R-type instructions)
funct: the function
together, op and funct tell the computer which operation to perform
shamt: the shift amount for shift instructions, otherwise it is 0

7. R-Type Examples Note the order of registers in the assembly code:
add rd, rs, rt

8. I-Type instructions Immediate-type 3 operands: op: the opcode
rs, rt: register operands
imm: 16-bit two’s complement immediate

9. I-Type Examples
Note the differing order of registers in the assembly and machine codes:
addi rt, rs, imm
lw rt, imm(rs)
sw rt, imm(rs)

10. J-Type instructions Jump-type 26-bit address operand (addr)
Used for jump instructions (j)

11. Review: Instruction Formats

12. Microarchitecture
Microarchitecture: how to implement an architecture in hardware
This is sometimes just called implementation
Processor:
Datapath: functional blocks
Control: control signals

13. Parts of CPUs Datapath Control unit
The registers and logic to perform operations on them
Control unit
Generates signals to control datapath

14. Memory and I/O
Memories are connected to the data/control in and out lines
Example: register to memory ops
Will discuss I/O arrangements later

15. Basic Datapath Basic components of the CPU datapath
PC, Instruction Memory, Register File, ALU, Data Memory
Copyright © 2007 Elsevier

16. First: A “lightweight” ALU
Arithmetic Logic Unit = ALU

17. Lightweight ALU A lightweight ALU from textbook: F2:0 Function 000
3-bit function select (7 functions)
F2:0
Function
000
A & B
001
A | B
010
A + B
011
not used
100
A & ~B
101
A | ~B
110
A - B
111
SLT

18. Lightweight ALU: Internals
(light-weight version)
F2:0
Function
000
A & B
001
A | B
010
A + B
011
not used
100
A & ~B
101
A | ~B
110
A - B
111
SLT

19. Set Less Than (SLT) Example
Configure a 32-bit ALU for the set if less than (SLT) operation.
Suppose A = 25 and B = 32.
A is less than B, so we expect Y to be the 32-bit representation of 1 (0x ).
For SLT, F2:0 = 111.
F2 = 1 configures the adder unit as a subtracter. So = -7.
The two’s complement representation of -7 has a 1 in the most significant bit, so S31 = 1.
With F1:0 = 11, the final multiplexer selects Y = S31 (zero extended) = 0x
1 bit (MSB)

20. Next: A “full-feature” ALU

21. Arithmetic Logic Unit (ALU)
Full-feature ALU from COMP411: A B
5-bit ALUFN
Sub Bool Shft Math OP
0 XX A+B
1 XX A-B
X X
X X
X B<<A X B>>A
X B>>>A
X A & B
X A | B
X A ^ B
X A | B
Add/Sub
Bidirectional
Barrel
Shifter
Boolean
Sub
Bool
Shft
Math …
Flags V,C N
Flag R Z
Flag

22. Shifting Logic Shifting is a common operation For example:
applied to groups of bits
used for alignment
used for “short cut” arithmetic operations
X << 1 is often the same as 2*X
X >> 1 can be the same as X/2
For example:
X = 2010 =
Left Shift:
(X << 1) = = 4010
Right Shift:
(X >> 1) = = 1010
Signed or “Arithmetic” Right Shift:
(-X >>> 1) = ( >>> 1) = = -1010 1 R7 R6 R5 R4 R3 R2 R1 R0 X7 X6 X5 X4 X3 X2 X1 X0
“0”
SHL1

23. Shifting Logic How do you shift by more than 1 position?
feed other bits into the multiplexer
e.g., left-shift-by-2
multiplexer for Rk receives input from Xk-2
How do you allow the shift amount to be specified dynamically?
need a bigger multiplexer
shift amount is applied as the select input
will design in class and lab

24. Boolean Operations
It will also be useful to perform logical operations on groups of bits. Which ones?
ANDing is useful for “masking” off groups of bits.
ex & = (mask selects last 4 bits)
ANDing is also useful for “clearing” groups of bits.
ex & = (0’s clear first 4 bits)
ORing is useful for “setting” groups of bits.
ex | = (1’s set last 4 bits)
XORing is useful for “complementing” groups of bits.
ex ^ = (1’s invert last 4 bits)
NORing is useful for.. uhm…
ex # = (0’s invert, 1’s clear)

25. Boolean Unit
It is simple to build up a Boolean unit using primitive gates and a mux to select the function.
Since there is no interconnection between bits, this unit can be simply replicated at each position.
The cost is about 7 gates per bit. One for each primitive function, and approx 3 for the 4-input mux. Ai Bi Qi
Bool
This logic block is repeated for each bit (i.e. 32 times)

26. An ALU at last! Full-feature ALU from COMP411: A B R 5-bit ALUFN
Sub Bool Shft Math OP
0 XX A+B
1 XX A-B
X X
X X
X B<<A X B>>A
X B>>>A
X A & B
X A | B
X A ^ B
X A | B
Add/Sub
Bidirectional
Barrel
Shifter
Boolean
Sub
Bool
Shft
Math …
Flags V,C N
Flag R Z
Flag

27. Which one do we implement?
We will use the full-feature one!
slightly more challenging …
I will help you!
… but a lot more fun to use
supports much more useful set of instructions for your final programming project

28. Processor Architecture
Rather, “microarchitecture”
or implementation

29. Microarchitectures Multiple implementations for a single architecture:
Single-cycle
Each instruction executes in a single cycle
Multicycle
Each instruction is broken up into a series of shorter steps
Pipelined
Each instruction is broken up into a series of steps
Multiple instructions execute at once.
Directly impacts performance obtained

30. Processor Performance
Program execution time
Execution Time = (# instructions) (cycles/instruction)(seconds/cycle)
Definitions:
Cycles/instruction = CPI
Seconds/cycle = clock period
1/CPI = Instructions/cycle = IPC
Challenge is to satisfy constraints of:
Cost
Power
Performance

31. MIPS Processor
We will consider a subset of MIPS instructions (in book & lab):
R-type instructions: and, or, add, sub, slt, …
Memory instructions: lw, sw, …
Branch instructions: beq, …
Some immediate instructions too: addi, …
Jumps as well: j, …

32. Next Next class: Lab Friday (March 30) We’ll look at single cycle MIPS
Then the more complex versions
Lab Friday (March 30)
Demo your graphics displays (Lab 8)
Start on Lab 9 (will post on website by Fri)
start building the datapath!
ALU
Registers