1. Core Generator Software System

2. After completing this module, you will able to:
Describe the differences between LogiCORE™ and AllianceCORE solutions
Identify two benefits of using cores in your designs
Create customized cores by using the CORE Generator software system GUI
Instantiate cores into your HDL design
Run behavioral simulation on a design that contains cores
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3. What are Cores?
A core is a ready-made function that you can instantiate into your design as a black box
Cores can range in complexity
Simple arithmetic operators, such as adders, accumulators, and multipliers
System-level building blocks, such as filters, transforms, and memories
Specialized functions, such as bus interfaces, controllers, and microprocessors
Some cores can be customized
Intellectual Property (IP) is another term that is often used in association with cores. Cores are one type of IP.
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4. Benefits of Using Cores
Save design time
Cores are created by expert designers who have in-depth knowledge of Xilinx FPGA architecture
Guaranteed functionality saves time during simulation
Increase design performance
Cores that contain mapping and placement information have predictable performance that is constant over device size and utilization
The data sheet for each core provides performance expectations
Use timing constraints to achieve maximum performance
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5. Types of Cores
LogiCORE solutions
AllianceCORE solutions
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6. LogiCORE Solutions Typically customizable
Fully tested, documented, and supported by Xilinx
Many are pre-placed for predictable timing
Many are unlicensed and provided for free with Xilinx software
More complex LogiCORE solution products are licensed
VHDL and Verilog flow support for several EDA tools
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7. AllianceCORE Solutions
Point-solution cores
Typically not customizable (some HDL versions are customizable)
Sold and supported by Xilinx AllianceCORE solution partners
Partners can be contacted directly to provide customized cores
A free evaluation version of the module is available
You will need to contact the IP Center for licensing and ordering information
All cores are optimized for Xilinx; some are pre-placed
Typically supplied as an Electronic Design Interchange Format (EDIF) netlist
VHDL and Verilog flow support
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8. Sample Functions LogiCORE solutions AllianceCORE solutions
DSP functions
Time skew buffers, Finite Impulse Response (FIR) filters, transforms, and correlators
Math functions
Accumulators, adders, multipliers, integrators, trig functions, and square root
Memories
Pipelined delay elements, single- and dual-port RAM
Synchronous FIFOs
PCI™ core master and slave interfaces, PCI core bridge
AllianceCORE solutions
Peripherals
DMA controllers, programmable interrupt controllers, and UARTs
Communications and networking
ATM, Fibre Channel, and Ethernet MAC
Error Correction
CTC, 3GPP, Viterbi, and Reed-Solomon
Video and image processing
Standard bus interfaces
PCMCIA, USB, PCI, PCI Express® core
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9. CORE Generator Software System
A Graphical User Interface (GUI) allows central access to LogiCORE IP products, as well as
Data sheets
Customizable parameters
Interfaces with design entry tools
Creates instantiation templates for HDL-based designs
Web Links tab provides access to the Xilinx Website and the IP Center
The IP Center contains new cores to download and install
You always have access to the latest cores
To view information about AllianceCORE products, visit the IP Center on the Web at
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10. Launching the CORE Generator
The Core Generator is available as standalone application
Launched from Programs  Xilinx ISE Design Suite ISE Design Tools Tools  Core Generator
Can be launched from ISE Project Navigator.
Latest 12.1 PlanAhead software has Core Generator software integrated.
To learn more about the Architecture Wizard, refer to the “Architecture Wizard and PinAhead” REL.
If you are not using the Project Navigator, enter coregen at a command prompt (UNIX shell or DOS box).
Demo Instructions:
To open an existing project in the ISE software: Select File > Open Project.
Browse to one of the lab project directories.
Select an ISE® software file and click Open.
Follow the instructions in the slide above to open the CORE Generator software.
Enter a file name and click Next.
Select a type of core, click Next, then click Finish.
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11. Running the CORE Generator
From the Project Navigator, select Project  New Source
Select IP (CORE Generator & Architecture Wizard) and enter a filename
Click Next and then select the type of core
To learn more about the Architecture Wizard, refer to the “Architecture Wizard and IOPlanner” REL.
If you are not using the Project Navigator, enter coregen at a command prompt (UNIX shell or DOS box).
Demo Instructions:
To open an existing project in the ISE software: Select File > Open Project.
Browse to one of the lab project directories.
Select an ISE® software file and click Open.
Follow the instructions in the slide above to open the CORE Generator software.
Enter a file name and click Next.
Select a type of core, click Next, then click Finish.
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12. Running the CORE Generator(contd)
From the PlanAhead GUI , select Project Manager IP Catalog.
In IP Cores window expand tree and select the type of core.
Demo Instructions:
To open an existing project in the PlanAhead software: Select Window > IP catalog.
Follow the instructions in the slide above to open the CORE Generator software.
Select a type of core, click Next, then click Finish.
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13. Core Customize Window Version information
Symbol (unused ports grayed out)
Customizable parameters spread over several dialog boxes
Data sheet access
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14. Core Data Sheets Features Also: Functionality and pinout (next page)
The Resource Utilization section of the data sheet may contain a table for cores that can be customized as well as resource utilization for common configurations.
Depending on the core and its customization, the performance expectations and resource utilization can vary.
For some cores performance and device utilization examples are included with the data sheet.
Performance expectations and resource utilization
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15. HDL Design Flow
compxlib.exe
Instantiate
Simulate
.VHD, .V
Implement
.VHO, .VEO
Generate Core
.xco
Compile library for behavioral simulation (one time only)
XilinxCoreLib
Core generation and integration
.NGC
The next few slides describe each step in the HDL flow in more detail.
The XCO file is a log of the options used to create the core. You can use this file to confirm that the correct options were used during core generation. You can also use this file to create another core with the same options. This file can also be used in batch mode.
In Project Navigator, the XCO file is automatically added to the project.
In the Language Templates, the instantiation templates will be added. To see the templates, select Edit > Language Templates or click the Language Templates icon in the horizontal toolbar.
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16. Core Generation and Integration
Generate or purchase a core
Netlist file (NGC)
Instantiation template files (VHO or VEO)
Behavioral simulation wrapper files (VHD or V)
Instantiate the core into your HDL source
Cut and paste from the templates provided in the VEO or VHO file
The design is ready for synthesis and implementation
Use the wrapper files for behavioral simulation
The ISE® software automatically uses wrapper files when cores are present in the design
VHDL: Analyze the wrapper file for each core before analyzing the file that instantiates the core
Instantiation template files provide a template with all of the correct port declarations for the core.
Simply cut and paste the template into your source file, change the instance name, if desired, and replace the dummy signal names with your own signal names.
During synthesis, the core will be treated as a black box. However, the NGC or EDIF file will be read in by the synthesis tool to analyze the timing of the interface to the core. If the NGC/EDIF is not in the project directory (which it is, by default), be sure to add the directory to the “Cores Search Directories” property of xst (-sd), or add the NGC/EDIF file to your synthesis tool.
During the first stage of implementation, the Xilinx tools will read in the NGC or EDIF file that was created by the CORE Generator software system. Again, if the core is not in the project directory, be sure to add the directory to the “Macro Search Path” property of translate (-sd).
Many VHDL simulators require lower-level files to be analyzed before the file that references them. Remember to analyze the wrapper files for your cores before you analyze the file that references them.
Most Verilog simulators do not have this order dependency.
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17. Compile the Simulation Library
Before your first behavioral simulation, you must run compxlib.exe to compile the XilinxCoreLib simulation library
Located in the $XILINX\bin\<platform> directory
Supports Mentor Graphics ModelSim and SpeedWave, Cadence NC-Verilog, and Synopsys VCS and Scirocco simulation tools
If you download new or updated cores, additional simulation models will be automatically extracted during installation
If you are using a simulator that is not supported by the compxlib.exe script, refer to the CORE Generator Guide and your simulator documentation for information on how to compile the XilinxCoreLib library.
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18. Summary
A core is a ready-made and verified function that you can insert into your design
LogiCORE solution products are sold and supported by Xilinx
AllianceCORE solution products are sold and supported by AllianceCORE solution partners
Using cores can save design time and provide increased performance
Cores can be used in schematic or HDL design flows
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19. Where Can I Learn More? Xilinx IP Center Xilinx Training
Help  Xilinx on the Web  IP Center
Find out about new IP (for EDK as well)
Browse IP by type, vendor, and function
Find IP documentation
Update the Core Generator with the latest IP
Evaluate IP
Xilinx Training
Xilinx tools and architecture courses
Hardware description language courses
Basic FPGA architecture, Basic HDL Coding Techniques, and other free training videos!
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20. Trademark Information
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