1. Architecture Wizard and I/O Planning Xilinx Training

2. Objectives After completing this module, you will be able to: List at least two uses for the Architecture Wizard Identify two features of the I/O Planner Create quality pin assignments for Xilinx FPGAs

3. Architecture Wizard Contains Several Wizards Use the command Project > New Source –Select IP (CORE Generator & Architecture Wizard) –Enter File name and click Next –Select components by function or name Wizards available for clocking, RocketIO serial transceivers, and memory interfaces

4. Clocking Wizard Helps You Define the DCM Main window –Select Clocking Features –Specify input clock Input Clock frequency Input Jitter

5. Specify Output Settings Specify output clock settings

6. Specify I/O and Feedback Select optional inputs / outputs and feedback

7. DCM Attributes Specify DCM attributes

8. Attributes are Written into the HDL Files by Default

9. Launching the I/O Planner from the Project Navigator Assign package pins before or after synthesis –Pins can be assigned before synthesis to test pin assignments Make sure assignments follow the I/O Banking Rules Avoid ground bounce problems with Simultaneous Switching Output (SSO) analysis Make sure assignments are appropriate for signals going to/from dedicated hardware Pin assignments are stored in your designs UCF

10. The I/O Planner is a Pin Assignment Editor Within the PlanAhead Tool The PlanAhead software is automatically installed with the ISE® software and it includes the I/O Planner at no extra cost The I/O Planner allows you to assign package pins before synthesis or implementation –This requires rules based I/O assignments DRC provides guidance for pin assignments connecting to dedicated FPGA logic (memory controllers, GTs, or differential pairs, for example) –Semi or fully automatic pin assignment capabilities Xilinx recommends that you place timing-critical ports before allowing automatic pin assignment of the remaining pins –Supports grouping related pins to simplify I/O interface management

11. I/O Planner GUI

12. Key Features The I/O Planner allows you to view both the die and the package views so that you can understand the I/O bank relationship with your logic

13. Package View The colored areas between the pins displays the I/O Banks Show Differential Pairs Global Clock pins Vcc GND No connect

14. Using the Package Viewer The Package Pin Viewer has a very detailed list –Uses both colors and symbols Display includes –Pin name (signal name, if assigned) –Pin number (E6, if unassigned) –Pin type (I/O) –Differential pair type (N) –Bank number (0) Pin Type: IO_L21N_0, Bank Number: 0

15. Key Features Final pin assignments can be exported in a CSV format (PCB schematic symbol), HDL, or UCF Cross highlighting of pins, I/O banks, package pins, and device resources is supported throughout Importing existing pin assignments is supported –So if you are having a problem, it is not too late for help from the I/O Planner SSN analysis allows you to find I/O banks where you may be close to creating a ground bounce problem –This feature is customizable for your board

16. Other Features SSN Results

17. Viewing Pin Compatibility The original chosen package of choice was XC5VLX330-FF1760 –To make it pin compatible simply right-click in the package viewer Modified package view after pin compatibility is applied with XC5VLX110- FF1760

18. I/O Layout Guidelines Control Signals Data Buses Data Flow Control signals enter in the center column Data pins are placed in the remaining columns Data flow is horizontal Can sometimes be vertical, but not common Clock regions tend to group logic

19. LSB MSB Data Bus Layout Follow bit ordering Disperse simultaneous switching outputs –Helps avoid ground bounce –Insert other unrelated bits in between binary encoded output pins

20. Interleaved Bus Layout Arithmetic functions involving two or more buses will benefit from interleaved pin constraints –For example C <= A + B; or C <= A * B; –Both buses follow bit ordering A(0) B(0) A(1) B(1) A(2) B(2) A(3) B(3)

21. Summary The Architecture Wizard consists of several wizards, including –Clocking Wizard –RocketIO Wizard –Memory Interface Generator These wizards make it easy for you to optimize your design to the dedicated resources in your FPGA The I/O Planner makes it easy for you to make good pin assignments that enhance your system speed and help you avoid common mistakes –Avoid ground bounce –Follow I/O banking rules –Comprehensive DRC

22. Where Can I Learn More? Architecture Wizard –More Info buttons in dialog boxes Xilinx online documents –www.support.xilinx.com Spartan-6 FPGA User guide Virtex-6 FPGA User guide PlanAhead User Guide –From the I/O Planner: Help > User Guide > PlanAhead User Guide

23. Where Can I Learn More? Xilinx Education Services courses –www.xilinx.com/training Xilinx tools and architecture courses Hardware description language courses Basic FPGA architecture and other topics

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