1. What Design Techniques Help Avoid Routing Congestion?
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2. Objectives After completing this module, you will be able to:
Explain the causes of routing congestion problems
Use design techniques that optimize routing before a routing congestion problem develops
Not everyone will have a routing problem, it will vary by application.
Xilinx continues to focus on fine tuning software algorithms to improve routing optimization.

3. Higher Bandwidth Applications
There is an increasing need for higher bandwidth and increased device utilization in Virtex-6 applications
Many applications require large amounts of data to be buffered to support high bandwidths generated by the SerDes features
This can create routing challenges and congestion that can impact timing closure
Not every design will be impacted, but it is better to build a better design sooner, rather than later
Virtex-6 has three types of local routing resources
Single, double, and quad which connect to one, two, and four CLBs away
They have been optimized for performance and power
Designs with a high number of control signals or high-fanout nets make routing more difficult
The problem has to do with routing to/from CLBs. The CLB resources are very flexible and some applications of the resources can tend to use a lot of routing around certain CLBs. But just like with any design, if you manage your control signal usage you can save a lot of routing resources.

4. Routing Congestion Symptoms
The design fails to route with NO warnings in PAR that detail specific nets that could not be routed
PAR issues this warning…
PAR Warning #464
The router has detected very dense, congested design. It is extremely unlikely the router will be able
to finish the design and meet your timing requirements. To prevent excessive run time the router will
change strategy. The router will now work to completely route this design but not to improve timing.
This behavior will allow you to use the Static Timing Report and FPGA Editor to isolate the paths with
timing problems. The cause of this behavior is either overly difficult constraints, or issue with the
implementation of synthesis of logic in the critical timing path. If you are willing to accept a long run
time, set the option “-xe c” to override the present behavior.
Routing congestion is usually experienced in one of three ways.

5. Routing Congestion Symptoms
Another symptom is a series of “intermediate status” stages reported by PAR
intermediate status: unrouted: Real time: 3 hrs 11 mins 59 secs
intermediate status: unrouted: Real time: 3 hrs 41 mins 51 secs
intermediate status: unrouted: Real time: 4 hrs 11 mins 47 secs
intermediate status: unrouted: Real time: 4 hrs 11 mins 44 secs
In this example, many unrouted nets continue to occur at considerably high levels. This indicates that the algorithms are not able to help enough to complete PAR or meet your timing constraints.

6. Reduce Sets, Resets, and CEs
Routing can be considered one of the most valuable resources
Secondary Control Signals compete for the same resources as the rest of the active signals of the design
Including timing-critical paths
More available routing gives the tools a better chance to meet your timing objectives
You can see how much fanout a typical reset can have. This is probably the biggest reason to remove resets from your design.
Can you migrate a reset to the global routing resources? Yes. Instantiate the STARTUP_VIRTEX6 component from the Xilinx Unified Library, add an IBUFG and connect it to the GSR input to the block, and assign the pin to a dedicated clock pin.
The designer must also be aware that the tools will not automatically move resets to dedicated clock pins, and that they have to control this.
Note that in the past, the implementation tools would infer the GSR signal for true global set/resets automatically. The implementation tools do not do this any more.
Tip: Using the GSR saves routing resources

7. Global Reset Net
The GSR input is an active-high global set/reset net that is active at the end of configuration
It uses a dedicated routing resource for signal distribution
Saves general interconnect
It can also be used to restore the initial state of the FFs in the FPGA at any time (although not recommended)
The initial state is communicated with an INIT attribute
It drives the output FFs for each block RAM, but does not affect the contents of each memory or SRL
Its routing delay is NOT characterized
It is connected to all synchronous elements through a wired OR gate
This allows a local reset to also drive the FF’s set/reset port
The Startup block also gives users access to the Global Tri-State net and configuration clock.

8. Getting By
Some designs can get away without any resets but many designs need some resets
Very few designs require resets on all registers, but most designers want a global reset after initialization
Most ASIC emulation also requires a described reset on every register.
Implement this global reset with the built-in Global Set/Reset (GSR)
GSR is good for initializing the values of your synchronous elements (FFs, Block RAMs)
Delay of GSR is slow (3 clock cycles after configuration) so use it after configuration, but don’t reset again unless you can tolerate the entire design being reset
Xilinx suggests that you selectively remove resets, or even better, selectively put them in.
You can tell that you have used sufficient resets when your design simulates properly. If you can functionally simulate an RTL design, it should work in the FPGA.

9. Inferring an Initialization (XST only)
If you have a reset, you can initialize all registers in VHDL / Verilog code
SR will cause the flip-flop to be set to the state inferred here
Inference is supported only for data types std_logic, bit_vector, bit, but NOT integer
This is helpful for RTL simulation of the design
If it functions during simulation, it should function on the FPGA
Note…if you design without a reset in your design, you still get a free global reset
This is an example of initialization. Synthesis tools do react on this code. Most people assume that this un-synthesizable code, but it will affect the init value of the register because that is tied to the registers primitive.
This code will reset to a 0 when the GSR is released after configuration. This way, you can have a known value in your chip.
This will also simulate to a 0 for start up during a functional simulation. If you do not do this and you have a counter, you will have Xs counting +1 and all you have is an x-counter. But if you use this with a counter or anything else, it will start with a known value.
This is mandatory if you design without a reset.
Note that this inference is currently not supported for Spartan-6.
Inferring an initial value only works for data types of std_logic, bit_vector, bit, but NOT integer.
Don’t forget that the SRL should not be initialized in your HDL (it will come up by default as 0).
In the VHDL example, the signal my_register will only become a register if used in conjunction with a clock. For example, my_register <= new_information when rising_edge(clk); Otherwise, my_register could just become wires in which the initial value will only appear for a short time during simulation and have no effect in implmentation.
VHDL:
signal my_regsiter : std_logic_vector (7 downto 0) := (others <= ‘0’);
Verilog:
reg [7:0] my_register = 8’h00;

10. Minimizing the Use of DCMs or PLLs
Case A – Embedded DCM
In-1
In-x
In-1
In-x
Case B – External DCM
DCM
DCM or PLL
Logic and Flip-flops
DCMs are a limited resource
Using fewer DCMs saves global clock buffers
Pulling buried DCMs or PLLs up to the top level reduces the resources the clocking resources your design will use

11. Global Clock Enable
To gate entire clock domains for power reduction, use the clock-enabled global buffer resource BUGCE or the BUFHCE
For applications that only pause the clock on small areas of the design, use the clock enable pin of the FPGA register
This saves general routing resources
Tip: This will save routing resources
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12. Summary
Designs with a high number of control signals or high-fanout nets make routing more difficult
Pulling buried DCMs or PLLs up to the top level
Use the GSR on power-up to reset your circuit into a known state
The GSR is used after configuration, every time
Don’t use it to reset the circuit during normal operation
Build your HDL code properly to infer an initialization value
Use the built-in CE features of the BUFHCE and the BUFGCE

13. Where Can I Learn More? Xilinx online documents
PlanAhead User Guide, UG632
Display design metrics
Floorplanning Methodology Guide, UG633
How to re-use placement information (Re-use Flow)
Retargeting Guidelines for Virtex-5 FPGAs, WP248
Helpful resource to clarify HDL coding techniques
Command Line Tool User Guide, UG628
How to run SmartXplorer with congestion reduction strategies

14. Where Can I Learn More?
Xilinx Education Services courses
Designing with Spartan-6 and Virtex-6 Device Families course
How to get the most out of both device families
How to build the best HDL code for your FPGA design
How to optimize your design for Spartan-6 and/or Virtex-6
How to take advantage of the newest device features
Free Video-based Training
How To Create Area Constraints with PlanAhead
What are the Benefits of PlanAhead?
How do I Resolve Routing Congestion?

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