1. Core Generator Software System

2. Describe the differences between LogiCORE™ and AllianceCORE solutions Identify two benefits of using cores in your designs Create customized cores by using the CORE Generator software system GUI Instantiate cores into your HDL design Run behavioral simulation on a design that contains cores After completing this module, you will able to:

3. A core is a ready-made function that you can instantiate into your design as a black box Cores can range in complexity –Simple arithmetic operators, such as adders, accumulators, and multipliers –System-level building blocks, such as filters, transforms, and memories –Specialized functions, such as bus interfaces, controllers, and microprocessors Some cores can be customized What are Cores?

4. Save design time –Cores are created by expert designers who have in-depth knowledge of Xilinx FPGA architecture –Guaranteed functionality saves time during simulation Increase design performance –Cores that contain mapping and placement information have predictable performance that is constant over device size and utilization –The data sheet for each core provides performance expectations Use timing constraints to achieve maximum performance Benefits of Using Cores

5. LogiCORE solutions AllianceCORE solutions Types of Cores

6. Typically customizable Fully tested, documented, and supported by Xilinx Many are pre-placed for predictable timing Many are unlicensed and provided for free with Xilinx software –More complex LogiCORE solution products are licensed VHDL and Verilog flow support for several EDA tools LogiCORE Solutions

7. Point-solution cores –Typically not customizable (some HDL versions are customizable) Sold and supported by Xilinx AllianceCORE solution partners –Partners can be contacted directly to provide customized cores –A free evaluation version of the module is available You will need to contact the IP Center for licensing and ordering information All cores are optimized for Xilinx; some are pre-placed Typically supplied as an Electronic Design Interchange Format (EDIF) netlist VHDL and Verilog flow support AllianceCORE Solutions

8. LogiCORE solutions –DSP functions Time skew buffers, Finite Impulse Response (FIR) filters, transforms, and correlators –Math functions Accumulators, adders, multipliers, integrators, trig functions, and square root –Memories Pipelined delay elements, single- and dual- port RAM Synchronous FIFOs PCI™ core master and slave interfaces, PCI core bridge Sample Functions AllianceCORE solutions –Peripherals DMA controllers, programmable interrupt controllers, and UARTs –Communications and networking ATM, Fibre Channel, and Ethernet MAC Error Correction CTC, 3GPP, Viterbi, and Reed-Solomon –Video and image processing –Standard bus interfaces PCMCIA, USB, PCI, PCI Express® core

9. A Graphical User Interface (GUI) allows central access to LogiCORE IP products, as well as –Data sheets –Customizable parameters Interfaces with design entry tools –Creates instantiation templates for HDL-based designs Web Links tab provides access to the Xilinx Website and the IP Center –The IP Center contains new cores to download and install You always have access to the latest cores CORE Generator Software System

10. The Core Generator is available as standalone application –Launched from Programs  Xilinx ISE Design Suite  ISE Design Tools  Tools  Core Generator Can be launched from ISE Project Navigator. Latest 12.1 PlanAhead software has Core Generator software integrated. Launching the CORE Generator

11. From the Project Navigator, select Project  New Source Select IP (CORE Generator & Architecture Wizard) and enter a filename Click Next and then select the type of core Running the CORE Generator

12. From the PlanAhead GUI, select Project Manager  IP Catalog. In IP Cores window expand tree and select the type of core. Running the CORE Generator (contd)

13. Core Customize Window Version information Symbol (unused ports grayed out) Customizable parameters spread over several dialog boxes Data sheet access

14. Core Data Sheets Features Also: Functionality and pinout (next page) Performance expectations and resource utilization

15. HDL Design Flow Compile library for behavioral simulation (one time only) Core generation and integration XilinxCoreLib.NGC compxlib.exe Instantiate Simulate.VHD,.V Implement.VHO,.VEO Generate Core.xco

16. Generate or purchase a core –Netlist file (NGC) –Instantiation template files (VHO or VEO) –Behavioral simulation wrapper files (VHD or V) Instantiate the core into your HDL source –Cut and paste from the templates provided in the VEO or VHO file The design is ready for synthesis and implementation Use the wrapper files for behavioral simulation –The ISE® software automatically uses wrapper files when cores are present in the design –VHDL: Analyze the wrapper file for each core before analyzing the file that instantiates the core Core Generation and Integration

17. Before your first behavioral simulation, you must run compxlib.exe to compile the XilinxCoreLib simulation library –Located in the $XILINX\bin\ directory –Supports Mentor Graphics ModelSim and SpeedWave, Cadence NC-Verilog, and Synopsys VCS and Scirocco simulation tools If you download new or updated cores, additional simulation models will be automatically extracted during installation Compile the Simulation Library

18. A core is a ready-made and verified function that you can insert into your design LogiCORE solution products are sold and supported by Xilinx AllianceCORE solution products are sold and supported by AllianceCORE solution partners Using cores can save design time and provide increased performance Cores can be used in schematic or HDL design flows Summary

19. Xilinx IP Center –Help  Xilinx on the Web  IP Center Find out about new IP (for EDK as well) Browse IP by type, vendor, and function Find IP documentation Update the Core Generator with the latest IP Evaluate IP Xilinx Education Services courses –www.xilinx.com/training Xilinx tools and architecture courses Hardware description language courses Basic FPGA architecture, Basic HDL Coding Techniques, and other free RELs! Where Can I Learn More?

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