1. Unit VI : Semiconductor Integrated Circuit Design
VLSI Design
13/03/2009
VLSI Design

2. Out Line Design Methodologies Full Custom Semi Custom Gate Arrays PLAs
FPGAs
13/03/2009
VLSI Design

3. IC Products Processors Memory chips Analog Programmable
CPU, DSP, Controllers
Memory chips
RAM, ROM, EEPROM
Analog
Mobile communication, audio/video processing
Programmable
PLA, FPGA
Embedded systems
Used in cars, factories
Network cards
System-on-chip (SoC)
Digital Signal Processing (DSP) chips are used all over the place: audio, image processing, satellite applications, etc.
Memory performance always behind CPU speed, greater need for more capacity, bandwidth
Network processors: low-cost, versatile, fast designs needed for the increasing internet applications, protocols, etc.
Images: amazon.com
13/03/2009
VLSI Design

4. Four Phases in Creating a Chip
13/03/2009
VLSI Design

5. Design Domains Behavioral Structural Physical (geometrical)
what a system does
Structural
how entities are connected together to perform the behavior
Physical (geometrical)
how to build a structure that has the required connectivity to implement the prescribed behavior
13/03/2009
VLSI Design

6. 13/03/2009
VLSI Design

7. VLSI Design Styles
13/03/2009
VLSI Design

8. Activity Sketch a stick diagram for a 4-input NOR gate 13/03/2009
VLSI Design

9. Simple Inverter Layout
13/03/2009
VLSI Design

10. Full-Custom Design
13/03/2009
VLSI Design

11. 1. Full-Custom Methodology
Custom design involves the entire design of the IC, down to the smallest detail of the layout.
Each transistor and each wire is individually defined by a set of polygons which are then used to generate the photographic masks needed in the fabrication process.
13/03/2009
VLSI Design

12. Full-Custom Design
Full-custom blocks are carefully crafted in the physical level to obtain the highest possible performance.
13/03/2009
VLSI Design

13. Full Custom Design
Using Full-Custom Design we can get exactly what we want.
However:
1) Complex to design
2) Takes weeks to fabricate
13/03/2009
VLSI Design

14. Full Custom Design ... Component Design Structural/RTL Description
Mem
Ctrl
Comp. Unit
Reg File
Place & Route
A/D
PLA
I/O
comp
RAM
A team of engineers work on each component of the system
After each component is designed / tested / optimized, put together the whole thing
Automatic tools might be used in each of the stages
...
13/03/2009
VLSI Design

15. Semi custom Design HDL Programming Structural/ RTL Description
Mem
Ctrl
Comp. Unit
Reg File
HDL Programming
P_Inp: process (Reset, Clock)
begin
if (Reset = '1') then
sum <= ( others => '0' );
input_nums_read <= '0';
sum_ready <= '0';
add82 : kadd8 port map (
a => add_i1, b => add_i2,
ci => carry, s => sum_o);
Mult_i1 <= sum_o(7 downto 0); D C B A
Designers describe the hardware in high-level languages such as VHDL and Verilog
A lot of automation is used (and the quality of the chip won’t be as good as full-custom – maybe up to 20x worse)
The cell library is developed by CAD companies. It contains gates such as AND, OR, XOR, or could even offer more complex cells such as adders and multipliers. C D A B
Cell library
Floorplan [©Sherwani]
13/03/2009
VLSI Design

16. Full-Custom Design Key Issues
Manual full-custom design can be very challenging and time consuming
Development cost are too high!
Full-custom design is used only in the critical blocks.
13/03/2009
VLSI Design

17. Semi-Custom Design
13/03/2009
VLSI Design

18. Semicustom Design Flow
HDL
Logic Synthesis
Floorplanning
Placement
Routing
Tape-out
Circuit extraction
Pre-Layout verification
Post-Layout simulation
Structural
Physical
Behavioral
Design Capture
Design Iteration
13/03/2009
VLSI Design

19. Cell-Based Design
All of the commonly used logic cells are developed, characterized, and stored in a standard cell library.
Library contains a certain numbers of basic cells such as inverters, NAND, NOR, each in several versions to provide a range of performance.
Most popular because of CAD tools availability and capability.
13/03/2009
VLSI Design

20. Standard Cells Methodology
A closely related technique is standard cell design in which large parts of the design have been performed ahead of time or possibly used in previous designs.
Standard cell implementation compared to full custom design ?
lower density
lower performance
However
Shortens the development cycle by allowing standard cells or pre-determined components to be used as building blocks from which large logic circuits can be constructed.
13/03/2009
VLSI Design

21. Standard Cells Methodology
Each standard cell contains a single gate of AND, OR, NOT etc.
All cells are the same height but vary in width.
Standard cells can be placed in rows and connected with wires that are placed in channels between rows.
13/03/2009
VLSI Design

22. Standard Cells All cells a fixed height (variable width)
Provide Vdd, Gnd to lines to connect by abutment, overlap
Cells placed in rows by placement program
Cells connected in channels by channel router
13/03/2009
VLSI Design

23. Standard Cells Methodology
Horizontal and vertical wires are generally fabricated on two different layers that are located above standard cells.
Standard cells are arranged into cell-libraries which are used by designers throughout design process.
Standard Cell
Routing Channel
13/03/2009
VLSI Design

24. Cell-based Design (or standard cells)
Functional
Module
(RAM,
multiplier, ) R o w s f C e l
Logic Cell
Routing
Channel
Feedthrough Cell
Routing channel
requirements are
reduced by presence
of more interconnect
layers
13/03/2009
VLSI Design

25. Example of Standard Cells
Power Rail
Ground Rail
Each cell layout is designed with a fixed height so that a number of cells can be “snapped” together side-by-side to form rows.
13/03/2009
VLSI Design

26. Standard Cells Use regular layout
Can automate the mapping process, but
Takes weeks to fabricate
No economies of scale
PWR
GND
CELL 1
CELL 2
CELL 3
CELL 4
CELL 5
CELL 6
ROUTING
Cells
PWR
GND
CELL 7
CELL 8
CELL 9
CELL 10
ROUTING
Cells
ROUTING
Cells
ROUTING
PWR
GND
CELL 11
CELL 12
CELL 13
CELL 14
CELL 15
CELL 16
Cells
ROUTING
13/03/2009
VLSI Design

27. Standard Cells Design Process
Design process for Standard Cells using CAD tools:
Schematic Capture
PC based schematic editor
Simulation
verify logic function and evaluate delays
Can get logic values for each signal or connection with respect to time.
13/03/2009
VLSI Design

28. Standard Cells Design Process(Cont..)
Placement
Onto Silicon surface
Row assignment for each cell and position of cell in each row.
i.e . minimise routing area by using a minimal number of routing tracks in each channel.
Routing
to connect all nets with wires of a minimum length.
13/03/2009
VLSI Design

29. Standard Cells implementation of a Full Adder
Standard cell implementation of a full adder.
See Truth table A B Ci S
Ci+1 1
13/03/2009
VLSI Design

30. Standard Cells implementation of a Full Adder
13/03/2009
VLSI Design

31. Standard Cells implementation of a Full Adder
13/03/2009
VLSI Design

32. Standard Cell Appropriate for all or part of a custom chip
All cells have the same height
Rows separated by routing channels
Channel height variable
Cell
Height
(includes
Vdd, Gnd)
Channel
height
13/03/2009
VLSI Design

33. Standard Cells … Library of common gates and structures (cells)
Decompose hardware in terms of these cells
Arrange the cells on the chip
Connect them using metal wiring …
13/03/2009
VLSI Design

34. Standard Cell – New Generation
Cell-structure
hidden under interconnect layers
13/03/2009
VLSI Design

35. What are Standard Cell Libraries
Standard-cell libraries are fixed set of well-characterized logic blocks.
Basic logic functions are used several times on the same integrated circuit.
It will have leaf cells ranging from simple gates to latches and flip-flops. These can then be used to build arithmetic blocks like adders and multipliers.
ASIC designers commonly employ the use of standard cell libraries due to their robustness and flexibility resulting in quick turnaround times.
13/03/2009
VLSI Design

36. Advantages of standard cell libraries
Designers save time and money by reducing the product development cycle time.
Reduce risk by using predesigned, pretested and precharacterised standard cell libraries.
Optimisation is possible.
13/03/2009
VLSI Design

37. Disadvantages of standard cell libraries
Time and expenses of designing or buying the standard cell library.
when the standard cell library must be ported to a new fabrication process, the physical layout of all the cells need to be changed.
13/03/2009
VLSI Design

38. Fragment of an ASIC Library
13/03/2009
VLSI Design

39. Gate Arrays .
13/03/2009
VLSI Design

40. Gate Array or Sea of Gates
This approach uses an IC that is partially prefabricated and is known as a gate array or sea of gates.
A pattern of gates fabricated in Si repeated thousands of times.
Entire chip contains identical gates
normally 3- or 4-input NAND or NOR gates.
10,000 – 1,000,000 gates can be fabricated within a single IC depending on the technology used.
All the gates are prefabricated only need to add the interconnections.
13/03/2009
VLSI Design

41. .
Gate array
A chip that contains a pre diffused but unconnected pattern of gates or gate components
Designer generates the details of the interconnection mask to characterize the array for their application.
13/03/2009
VLSI Design

42. Gate Array Transistors predefined
W/L all the same (or choice limited)
Transistors prefabricated
Chip covered with transistors (sea of gates)
Designer provides metal patterns that form logic gates by connecting transistors
Transistors under wiring channels not used. Why?
Cheaper and faster to manufacture than standard cells. Why?
13/03/2009
VLSI Design

43. Gate Arrays Completed array of gates without final metal
Metal specified by CAD Tools
Tradeoffs vs standard cells
faster turnaround
lower NRE (non-recurring engineering) cost
higher unit cost
VDD
Gnd
“Sea of Gates”
13/03/2009
VLSI Design

44. Gate Array
Since manufacture of interconnections requires only metal deposition
 cost of manufacturing gate arrays is substantially lower than it is for the custom approach
However, the density of gate arrays is lower than that of custom IC’s.
A gate array of the same size as a custom IC will contain 25% - 10% the number of gates as the corresponding custom IC.
13/03/2009
VLSI Design

45. Field Programmable Gate Array
More recently, VLSI approaches have been developed for PLD’s to handle designs that in the past were implemented by many small chips or with gate arrays 1,000 – 500,000 gates.
New approaches yield high capacity programmable logic devices typically called
Complex Programmable Logic Devices (CPLD’s)
Field Programmable Gate Arrays (FPGA’s)
13/03/2009
VLSI Design

46. Field-Programmable Gate Arrays (FPGAs)
Fixed array of gates
Electrically programmable interconnect
Tradeoffs: very low NRE, high unit cost
CLB
CLB
CLB
CLB
13/03/2009
VLSI Design

47. Field-Programmable Gate Arrays (FPGAs)
13/03/2009
VLSI Design

48. Field Programmable Gate Array
CPLDs and FPGAs two structures typically share the following properties
Substantial uncommitted combinational logic
Pre-implemented flip-flops
Programmable interconnects between the combinational logic, flip-flops and chip Inputs and Outputs
13/03/2009
VLSI Design

49. Field Programmable Gate Array
Aside from the properties common to all VLSI PLD’s, the devices differ significantly from Vendor to Vendor.
Altera MAX 7000 CPLD
Actel ACT 3 FPGA
Xilinx XC4000 Structure
13/03/2009
VLSI Design

50. Field Programmable Gate Array
Field Programmable Devices
Avoid fabrication cost and time associated with gate arrays
Trade off is lower gate density.
Field Programmable devices are arrays of logic components whose connectivity can be established simply by loading appropriate configuration data into device’s internal memory.
13/03/2009
VLSI Design

51. Field Programmable Gate Array
Since devices can be reprogrammed any number of times, they are well suited for use in the following designs:
new designs in which the design specification is evolving. i.e. design prototypes.
designs which must be customised for the user.
Small volume production.
13/03/2009
VLSI Design

52. Field Programmable Gate Array
Every FPGA contains
an array of programmable logic blocks (PLBs) surrounded by
programmable interconnects
several I/O blocks on the perimeter of the IC, which are used to drive other components that are located off the chip.
Each PLB consists of
two 4-input logic blocks
two 1-bit memory elements
13/03/2009
VLSI Design

53. FPGA Design Flow Detailed Design Ideas Device Programming Timing
Simulation
Synthesis &
Implementation
Functional
tpd=22.1ns
fmax=47.1MHz
FPGA
CPLD
13/03/2009
VLSI Design

54. What’s Inside an FPGA? Logic Blocks - used to implement logic
- lookup tables and
flip-flops
Altera: LABs
Xilinx: CLBs
13/03/2009
VLSI Design

55. What’s Inside an FPGA? I/O Blocks - interface off-chip
- can usually support
many I/O Standards
13/03/2009
VLSI Design

56. What’s Inside an FPGA?
13/03/2009
VLSI Design

57. Field Programmable Gate Array (FPGA)
13/03/2009
VLSI Design
Architecture of Xilinx FPGAs

58. FPGA (Cont.) Simplified block diagram of a CLB by Xilinx 13/03/2009
VLSI Design
Simplified block diagram of a CLB by Xilinx

59. Diagram of Xilinx’s Configurable Logic Block
13/03/2009
VLSI Design
Diagram of Xilinx’s Configurable Logic Block

60. Examples of FPGA Structures from vendors:
Actel ACT3 FPGA Structure
13/03/2009
VLSI Design

61. Altera MAX 7000 FPGA Structure
13/03/2009
VLSI Design

62. ISE Alliance and Foundation Series Design Software
Xilinx
Primary products: FPGAs and the associated CAD software
Main headquarters in San Jose, CA
Fabless* Semiconductor and Software Company
UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}
Seiko Epson (Japan)
TSMC (Taiwan)
Programmable
Logic Devices
ISE Alliance and Foundation
Series Design Software
Source: [Xilinx Inc.]
13/03/2009
VLSI Design

63. 13/03/2009
VLSI Design

64. Xilinx FPGA Configurable Logic Blocks I/O Blocks Block RAMs Block RAMs
13/03/2009
VLSI Design

65. Block RAM Most efficient memory implementation
Spartan-3
Dual-Port
Port A
Port B
Most efficient memory implementation
Dedicated blocks of memory
Ideal for most memory requirements
4 to 104 memory blocks
18 kbits = 18,432 bits per block (16 k without parity bits)
Use multiple blocks for larger memories
Builds both single and true dual-port RAMs
The Block Ram is true dual port, which means it has 2 independent Read and Write ports and these ports can be read and/or written simultaneously, independent of each other. All control logic is implemented within the RAM so no additional CLB logic is required to implement dual port configuration.
The Altera 10KE and ACEX 1K families have only 2-port RAM. To emulate dual port capability, they would need twice the number of memory blocks and at half the performance.
13/03/2009
VLSI Design

66. Xilinx FPGA Families Old families XC3000, XC4000, XC5200
Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs.
Low Cost Family
Spartan/XL – derived from XC4000
Spartan-II – derived from Virtex
Spartan-IIE – derived from Virtex-E
Spartan-3, Spartan 3E, Spartan 3L
High-performance families
Virtex (220 nm)
Virtex-E, Virtex-EM (180 nm)
Virtex-II, Virtex-II PRO (130 nm)
Virtex-4 (90 nm)
Virtex 5 (65 nm)
Source: [Xilinx Inc.]
13/03/2009
VLSI Design

67. Xilinx Altera FPGA families Low-cost High-performance
Spartan Virtex 4 LX / SX / FX
Spartan 3E Virtex 5 LX
Spartan 3L
Xilinx
Cyclone II Stratix II
Stratix II GX
Altera
13/03/2009
VLSI Design

68. Programmable Logic Blocks
Each logic block can be programmed to implement any Boolean function of four variables,
the functional value it generates could be either directly outputted to another PLB or can be stored for later use in a 1-bit memory element.
13/03/2009
VLSI Design

69. Programmable Logic Blocks
FPGA technology enables the designer to implement the full adder with one PLB,
Carry and Sum functions could each be implemented with one logic block.
NOTE : As the Carry and Sum functions are both 3-variable functions one input to each block is unused.
13/03/2009
VLSI Design

70. 13/03/2009
VLSI Design

71. 13/03/2009
VLSI Design

72. 13/03/2009
VLSI Design

73. DO-DI-DSP-DK2 ---- $2,495 (Resale) XtremeDSP Development Kit
DO-DI-DSP-DK2-SG --- $3,990 (Resale) XtremeDSP + System Generator for DSP
13/03/2009
VLSI Design

74. FPGA Design Program logic table for each logic block.
An FPGA chip provides thousands of logic gates, organized into logic blocks, with programmable interconnects.
To implement a custom hardware, a user can use high-level hardware programming (e.g., HDL).
Program logic table for each logic block.
Program interconnect switch matrices
Program I/O blocks
Programs last as long as the chip is powered-on
13/03/2009
VLSI Design

75. Benefits Of FPGA-Based Design
Improved product flexibility
Changes hardware/software up to (and even after) deployment
Inventoried parts can be re-deployed in multiple applications
More product variants on single platform
Upgrade/enhance in the field
Reduce inventory
Single part for multiple variations and versions of product
13/03/2009
VLSI Design

76. Granularity of the logic block - Size of logic block
FPGA Design Key Issues
Chip utilization of an FPGA depends on
Granularity of the logic block - Size of logic block
Routing capability - Size of switch matrices
The largest advantage of FPGA-based design is the very short turn-around time
The time required from the start of the design process until a functional chip is available
13/03/2009
VLSI Design

77. Programmable Logic Devices
Categories of prewired arrays (or field-programmable devices):
Fuse-based (program-once)
Non-volatile EPROM based
RAM based
13/03/2009
VLSI Design

78. Programmable Logic Devices
PAL
PLA
PROM
13/03/2009
VLSI Design

79. Design Flows
13/03/2009
VLSI Design

80. Two competing implementation approaches
FPGA
Field Programmable
Gate Array
ASIC
Application Specific
Integrated Circuit
designed all the way
from behavioral description
to physical layout
no physical layout design;
design ends with
a bitstream used
to configure a device
designs must be sent
for expensive and time
consuming fabrication
in semiconductor foundry
bought off the shelf
and reconfigured by
designers themselves
13/03/2009
VLSI Design

81. Which Way to Go? ASICs FPGAs Off-the-shelf High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes
Reconfigurability
13/03/2009
VLSI Design

82. ASIC Versus FPGA Comparison
Tooling cost
Non-recurring engineering costs (NRE)
Time to market
Product risk
Product flexibility
Inventory simplification
13/03/2009
VLSI Design

83. Digital Logic Implementation Alternatives
Full Custom
PWR
GND
CELL 1
CELL 2
CELL 3
CELL 4
CELL 5
CELL 6
CELL 8
CELL 7
CELL 10
CELL 9
Standard Cells
Gate Arrays
Field-Programmable Gate Arrays (FPGAs) i6 i5 i4 i3 i2 i1
Programmable Logic Devices o1
Discrete Components
13/03/2009
VLSI Design

84. Non-Recurring Engineering (NRE)
ASIC Designs
NRE for ASIC Designs ~$500K/run for .13µ
Each subsequent re-spin costs another NRE
For new 90nm technology NRE >$1M
High-risk methodology requiring massive volume to recoup costs
FPGA Designs
No NRE charges
Some cost-reduction available by ASIC conversion with minimal (<$100K) NRE
Cost of FPGA device is offset by NRE in all but the highest volume applications
13/03/2009
VLSI Design

85. Time To Market ASIC Designs FPGA Designs
Typical design cycle months, minimum 9 months
Additional re-spins add 8-10 weeks each
FPGA Designs
Typical design cycle 4 months
Re-spins not an issue
13/03/2009
VLSI Design

86. The Big Picture: IC Design Methods
Cost / Development
Time
Design Methods
Quality
% Companies involved
Full Custom
Standard Cell
Library Design
ASIC – Standard Cell Design
What is the difference between full custom and ASIC design?
Tools used in Full Custom would be Magic-like, and tools used in RTL-Level Design would be CAD tools for synthesis, PD, etc.
Since Full Custom costly (number of designers, design time, fabrication cost, scalability, etc.) only companies like Intel afford
This course will be related to the first two (possibly third) design methods.
RTL-Level Design
13/03/2009
VLSI Design

87. Optimization: Levels of Abstraction
Algorithmic
Encoding data, computation scheduling, balancing delays of components, etc.
Gate-level
Reduce fan-out, capacitance
Gate duplication, buffer insertion
Layout
Move transistors driven by late inputs closer to the output
Effectiveness
Level of detail
13/03/2009
VLSI Design

88. Computer Aided Design Design Tool Analysis and Verification Tool
Why do we need CAD tool?
complexity of circuit
CAD TOOLs
Design Tool
ie. schematic drawing packages
Analysis and Verification Tool
ie. SPICE
Synthesis Tool
generate low level of abstraction
13/03/2009
VLSI Design

89. Computer-Aided Design Technology
CAD tools become more and more indispensable for timely development of ICs.
Remember!  CAD tools are good helpers for time-consuming and computation intensive mechanistic parts of the design, not the creative and inventive parts!
CAD technology divides into three categories:
Synthesis Tools (Synopsys®)
Layout Tools (Cadence®)
Simulation and Verification Tools
13/03/2009
VLSI Design

90. Synthesis Tools Based on Hardware-Description Languages (HDL)
High-Level Synthesis tools automate the design phase in the top level of the design hierarchy:
Based on Hardware-Description Languages (HDL)
VHDL, Verilog, etc.
Determining the types and quantities of modules to be included in the design using accurate estimate of lower level design features (area and delay).
Logic Synthesis and optimization tools can then be used to customize the design to particular needs, such as area minimization, low power, etc.
13/03/2009
VLSI Design

91. Gate-level Netlist module carry(input a, b, c, output cout)
wire x, y, z;
and g1(x, a, b);
and g2(y, a, c);
and g3(z, b, c);
or g4(cout, x, y, z);
endmodule
13/03/2009
VLSI Design

92. Transistor-Level Netlist
module carry(input a, b, c,
output cout)
wire i1, i2, i3, i4, cn;
tranif1 n1(i1, 0, a);
tranif1 n2(i1, 0, b);
tranif1 n3(cn, i1, c);
tranif1 n4(i2, 0, b);
tranif1 n5(cn, i2, a);
tranif0 p1(i3, 1, a);
tranif0 p2(i3, 1, b);
tranif0 p3(cn, i3, c);
tranif0 p4(i4, 1, b);
tranif0 p5(cn, i4, a);
tranif1 n6(cout, 0, cn);
tranif0 p6(cout, 1, cn);
endmodule
13/03/2009
VLSI Design

93. SPICE Netlist .SUBCKT CARRY A B C COUT VDD GND
MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P
MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P
MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P
MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P
MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P
MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P
MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P
MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P
MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P
MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P
CI1 I1 GND 2FF
CI3 I3 GND 3FF
CA A GND 4FF
CB B GND 4FF
CC C GND 2FF
CCN CN GND 4FF
CCOUT COUT GND 2FF
.ENDS
13/03/2009
VLSI Design

94. Layout Tools
Circuit Optimization tools deal with the design in the transistor schematic levels:
Transistor sizing for delay minimization
Reliability issues: process variations, noise.
Layout tools concern with the physical level of the design, i.e., how circuits are actually built on the IC:
Standard Layout CAD tools are Floorplanning, Place-and-route, and Module generation
Sophisticated Layout CAD tools are goal driven and include some degree of optimization functions
13/03/2009
VLSI Design

95. Simulation and Verification Tools
Time spent on debugging and correcting a design has been increasing exponentially as each generation passed.
Higher penalty is paid if a design flaw is detected later in the design process.
Simulation and verification are the most mature area in VLSI CAD
Goal of all simulation tools is to determine if the design meets the required specifications at a particular design stage.
13/03/2009
VLSI Design

96. Simulation Tools (Cont.)
Simulation tools used at various stages of the design process are
Behavior simulation tools
Logic Level simulation tools
Complement logic synthesis and optimization tools.
Circuit-level simulation tools
SPICE or derivatives such as HSPICE, PSPICE, etc.
Design Rule Checking tools
Layout rule checking, Electrical Rule Checking (ERC), reliability rule checking.
13/03/2009
VLSI Design

97. Programmable Logic Device
A Programmable Logic Device is an integrated circuit with internal logic gates and interconnects. These gates can be connected to obtain the required logic configuration.
• The term “programmable” means changing either hardware or software configuration of an internal logic and interconnects.
• The configuration of the internal logic is done by the user.
• PROM, EPROM, PAL, GAL etc. are examples of Programmable Logic
13/03/2009
VLSI Design

98. Array-Based Programmable Logic5 4 O 3 2 1
Programmable
OR array O I 3 2 1
Fixed AND array
Programmable
OR array I 5 4 O 3 2 1
Fixed OR array
Programmable AND array
Programmable AND array O O O 3 2 1 O 3 O 2 O 1
PLA
PROM
PAL
Indicates programmable connection
Indicates fixed connection
13/03/2009
VLSI Design

99. Difference between CPLD and FPGA
13/03/2009
VLSI Design

100. Field Programmable Gate Array
• FPGA is a general purpose, multi-level programmable logic device
• FPGA is composed of,
- logic blocks to implement combinational and sequential
logic circuit
- programmable interconnect  wire to connect input and
output of logic blocks
- I/O blocks  logic blocks at periphery of device for the
external connection
•“The routing resources are both the greatest strength and weakness of FPGAs
13/03/2009
VLSI Design

101. PLA (Programmable Logic Array)
• array of AND and OR gates are programmable
• product term sharing: every product term of the AND array can be
connected to the input of any OR gate
• unidirectional input/output pins
PLA device
13/03/2009
VLSI Design

102. Programming Technologies
Programmable Logic Device can be programmed in two ways:
1. Mask programming (in some few cases)
2. Field programming (typical)
13/03/2009
VLSI Design

103. Mask programming
Mask programming: programming of device is done in the mask level.
+ good timing performance due to internal connections hardwired during
manufacture
+ cheap at high volume production
- programmed by manufacturer
- development cycle = weeks or months
- not re-programmable
13/03/2009
VLSI Design

104. Nonpermanent type (Volatile):
Programming Technologies (II)
Field programming: Programming of device is done by the user. The
programming technologies are of two types
Permanent type (Non-volatile):
• Fuse (normal on) - ‘CLOSE (intact)’ ‘OPEN (blown)’
• Anti-fuse (normal off) - just the opposite of a FUSE
• EPROM
• EEPROM
Nonpermanent type (Volatile):
• driving n-MOS pass transistor by SRAM
• NOTE:
-When power of device is switched off then the content of SRAM is lost.
13/03/2009
VLSI Design

105. - static RAM cells - anti fuse - EPROM transistor - EEPROM transistor
Programming Technologies
• Currently, there are four programming technologies for FPGAs,
- static RAM cells
- anti fuse
- EPROM transistor
- EEPROM transistor
13/03/2009
VLSI Design

106. Static RAM programming technology:
completely reusable - no limit concerning re-programmability
• pass gate closes when a “1” is stored in the SRAM cell
• allows iterative prototyping
• volatile memory - power must be maintained
• large area - five transistor SRAM cell plus pass gate
• memory cells distributed throughout the chip
• fast re-programmability (tens of milliseconds)
• only standard CMOS process required
13/03/2009
VLSI Design

107. Anti-fuse Programming
An anti-fuse is the opposite of normal fuse.
• Anti-fuse are made with a modified CMOS process having an extra step
• This step creates a very thin insulating layer which separates two
conducting layers
• That thin insulating layer is fused by applying a high voltage across the
conducting layer
• Such high voltage can be destructive for CMOS logic circuit
• Non-volatile (Permanent)
• Requires extra programming circuitry, including a programming
transistor
13/03/2009
VLSI Design

108. Actel PLICE Anti-fuse programming technology
The Actel PLICE anti-fuse consists of a layer of positively doped silicon (n+
diffusion), a layer of dielectric (Oxygen-Nitrogen-Oxygen) and a layer of
polysilicon
• it is programmed by placing a relatively high voltage (18V) across the antifuse
terminals which results current of about 5 mA through it
• typical resistance of a fused contact is 300 to 500 Ω
• manufactured by 3 additional masks to a normal CMOS process
programmable low-impedance circuit element (PLICE)
13/03/2009
VLSI Design

109. The Design Process Outline Goal Design Domain Design Flow
Behavioral Design
Structural Design
Physical Design
Management of Complexity
Goal
Understand phases of design process
Understand complexity management
Understand where tools are needed
13/03/2009
VLSI Design

110. Design Flow Design Specification Verify Function Behavioral Design
Sim., DRC
Verify Function
Mapping
Feedback
Structural
Design
Sim., DRC
Verification
Function
Speed, Power
Mapping
Physical
Design
Simulation
Design Rule Checking
Manuf.
Data
Manufacturing
Specification
13/03/2009
VLSI Design

111. Design Phase Upper Design Level Map to more detailed Synthesis
design representation.
Usually just
rework design
Determine if design meets
performance objectives,
obeys manufacturing rules.
Often contained as part of synthesis tool inner loop.
Analysis
Reject
Might require
starting over
Determine if equivalent to more abstract design. Human error or tool bug if not.
Verification
Validation
Reject
Lower Design Level
13/03/2009
VLSI Design

112. Behavioral Design Map design spec to formal behavioral description
design spec == user desires
“a cheap 100MHz Pentium chip”
often not formally described
design and behavioral spec often developed together
Approach
use behavioral hardware description language (HDL)
Verilog
VHDL
HDL is programming language superset
support for timing, modules
verify HDL implements design spec
usually through simulation
check that HDL is self-consistent
“compile” and simulate
13/03/2009
VLSI Design

113. Structural Design + Map behavioral spec to structural spec
partition into functional blocks - the netlist
targets for eventual physical design
Approach
use behavioral modules as starting point
decompose each block to finer detail
function to gates to transistors, etc.
stop at manufacturing interface
logic design - boolean equations => gates
simulation to verify structure has correct behavior
interconnect verification
design rule checking
feedback from physical design - back annotation
for performance verification
c = a + b
RegA
RegB +
RegC
No!
13/03/2009
VLSI Design

114. Physical Design Map from structure to physical implementation
target technology
technology mapping
netlist to 2-D layout
Approach
partition into boards, modules, chips, cells, layout
place and route
fix cell locations
route wiring
cell layout
design rule checking
circuit extraction
interconnect verification
back annotation
13/03/2009
VLSI Design

115. Management of Complexity
Bigger, faster designs have more coupling in design flow
more feedback => more design iterations => higher cost
simultaneous design => complex tools
cannot do “technology independent” design
Typical big design
10M transistors
300 MHz clock rate
beyond brute force approaches
Solutions
hierarchy
regularity
abstraction
simplification
13/03/2009
VLSI Design

116. Hierarchy Structure design as you would a program “procedure calls”
stop at manufacturing interface - “atoms” of IC universe
ALU
Shift
Reg
Mult µP
Datapath
Cache
I/O
1-Bit ALU
SRAM
Use ALU cell
from library •
Design SRAM
cell by hand •
13/03/2009
VLSI Design

117. Regularity Use replication Examples Enhancement
behavioral - call same procedure many times
structural - instantiate same cell many times
physical - instantiate same cell many times
Examples
bit in SRAM array
bit slice in datapath
Enhancement
module generators
procedure call for structural and physical design
pitch matching
array logic
PLA, ROM
13/03/2009
VLSI Design

118. Abstraction Use most abstract representation possible
hide information => less memory
simpler representation => less CPU time
to generate
to analyze!
Generate information only as needed
cost too high to generate and discard
Accuracy-cost tradeoff
never enough resources
for full verification
performance prediction
optimization
13/03/2009
VLSI Design

119. Simplification Restrict design space Restrict object types
restrict technology
only single-poly, double-metal CMOS
restrict circuit family
only digital
only complementary gates
restrict design style
only gate array
Restrict object types
only rectangular mask geometry
no overlapping layout cells
13/03/2009
VLSI Design

120. Implications for EDA Tool Design
Support the design flow
Limit domain
but tools also determine the design flow
but entire application range must be covered
Restrict representations
a tool box, not a Swiss Army knife
Bridge domains
verification - e.g. logic vs. layout
concurrent design
Bridge representations
verification - e.g. netlist vs. geometry
sufficient accuracy with acceptable speed
EDA tools must meet designer’s needs
13/03/2009
VLSI Design

121. References Digital Integrated Circuits - John M. Rabaey, PHI,
CMOS VLSI design, Neil H.E.Weste,David Harris,Ayan Banerjee
CMOS Digital Integrated Circuits Analysis And Design, Sung-mo Kang,Yusuf Leblebici
13/03/2009
VLSI Design

122. --Work constantly, work be not attached. Be not caught
--Work constantly, work be not attached. Be not caught. Reserve un to yourself the power detachment yourself from every thing, however beloved, however much the soul might yearn it, however the pangs misery you feel if you were going to leave it. Still, reserve the power of leaving it whenever you want.
---
13/03/2009
VLSI Design