1. CMOS Analog Design Using All-Region MOSFET Modeling
Chapter 10
Fundamentals of sampled-data circuits
CMOS Analog Design Using All-Region MOSFET Modeling

2. MOS sample-and-hold circuits
Basic MOS sample-and-hold circuit (the circuit implements a track-and-hold function, but we adopt the term sample-and-hold, the most commonly used in the literature)
CMOS Analog Design Using All-Region MOSFET Modeling
EMICRO II - Bahia

3. Thermal noise in S/H
Equivalent circuit of the S/H with the switch on and vi = 0.
Power spectral density of the noise voltage across the capacitor
CMOS Analog Design Using All-Region MOSFET Modeling

4. CMOS Analog Design Using All-Region MOSFET Modeling
Idealized sampling
CMOS Analog Design Using All-Region MOSFET Modeling

5. CMOS Analog Design Using All-Region MOSFET Modeling
Aliasing of thermal noise
The resistor noise power spectral density is multiplied by 2 fNB/fs: fs
2fNB f
The fully aliased thermal noise in the
(useful) Nyquist bandwidth -fs/2 < f < fs/2 is
Simplified representation of the aliasing of thermal noise due to sampling for the case 2fNB/fs = 6.
CMOS Analog Design Using All-Region MOSFET Modeling

6. CMOS Analog Design Using All-Region MOSFET Modeling
Thermal vs. quantization noise
Number of bits (B)
Capacitance (C) 8
3.3 fF 12
0.83 pF 14
13.3 pF 16
213 pF 20
55 nF
VFS= 1 V and T=300 K
Quantization error of digitized analog waveform. VFS is the full-scale voltage range and Δ is the size of the LSB
CMOS Analog Design Using All-Region MOSFET Modeling

7. CMOS Analog Design Using All-Region MOSFET Modeling
Switch on-resistance
Vin
Variation of the on-conductance of the nMOS, pMOS, and CMOS switches with the input voltage.
Illustration of the distortion produced by the input-dependent delay of the MOS S/H in the tracking mode
CMOS Analog Design Using All-Region MOSFET Modeling

8. Linearized S/H with output buffer
Linearization of the MOS sampling switch
Linearized S/H with output buffer
Sampling instant variation (a) ordinary S/H; (b) linearized S/H
CMOS Analog Design Using All-Region MOSFET Modeling

9. CMOS Analog Design Using All-Region MOSFET Modeling
Charge injection by the switch - 1
For
For ΔV = 1mV, calculate the maximum clock frequencies for effective channel length of 1 µm, µm and 100 nm µ = 500 cm2/V·s
Answer: fs : 10 MHz, 100 MHz, and 1 GHz, for 1 µm, µm, and 100 nm channel lengths, respectively.
CMOS Analog Design Using All-Region MOSFET Modeling

10. CMOS Analog Design Using All-Region MOSFET Modeling
Charge injection by the switch - 2
Charge injection cancellation techniques: (a) short fall time of
the clock and half-sized dummy switches, (b) fully-differential
structure
CMOS Analog Design Using All-Region MOSFET Modeling

11. CMOS Analog Design Using All-Region MOSFET Modeling
Low-voltage S/H circuits - 1
On-conductance of a CMOS switch for two different supply voltages: (a) VDD = 5V and (b) VDD = 1.5 V
CMOS Analog Design Using All-Region MOSFET Modeling

12. CMOS Analog Design Using All-Region MOSFET Modeling
Low-voltage S/H circuits - 2
(a) Available output swing obtained by dc-shifting the input signal applied to the n- and p-MOS switches (VDSsat is the voltage margin to either VDD or ground required for the proper operation of the blocks, e.g., amplifiers, connected to the switches); (b) Low-voltage S/H that provides dc bias for proper operation of both switches
CMOS Analog Design Using All-Region MOSFET Modeling

13. CMOS Analog Design Using All-Region MOSFET Modeling
Low-voltage S/H circuits - 3
Bootstrapped MOS switch: (a) Simplified schematic and (b) Input (source) and clock (gate) signals
CMOS Analog Design Using All-Region MOSFET Modeling

14. Jitter analysis
T is a random variable the standard deviation of which is called (aperture) jitter a, measured in (rms) seconds.
Typical clocks: jitter of 100 ps rms, high quality clocks jitter of 1 ps rms.
the signal-to-noise (SNR) of the S/H due to clock jitter is given by
CMOS Analog Design Using All Region MOSFET Modeling
CMOS Analog Design Using All-Region MOSFET Modeling 14

15. CMOS Analog Design Using All-Region MOSFET Modeling
Resolution vs. sampling rate in A/D
Resolution, in number of bits, as stated by the manufacturer, versus sampling rate, for A/D converters implemented in silicon
CMOS Analog Design Using All-Region MOSFET Modeling

16. CMOS Analog Design Using All-Region MOSFET Modeling
Basics of switched-capacitor (SC) filters
Thus, on average, the switched capacitor behaves as a resistor with its resistance value given by
CMOS Analog Design Using All-Region MOSFET Modeling

17. CMOS Analog Design Using All-Region MOSFET Modeling
First-order low-pass SC filter
CMOS Analog Design Using All-Region MOSFET Modeling

18. CMOS Analog Design Using All-Region MOSFET Modeling
Switched-capacitor integrators – 1
(a) Continuous-time and (b) parasitic-sensitive switched-capacitor integrators.
CMOS Analog Design Using All-Region MOSFET Modeling

19. (a) Non-inverting and (b) inverting parasitic-insensitive integrators
Switched-capacitor integrators – 2 v2 v1 C1 C2 1 2
(a)
(b)
(a) Non-inverting and (b) inverting parasitic-insensitive integrators
CMOS Analog Design Using All-Region MOSFET Modeling

20. (a) Elementary charge mirror and (b) Basic SC signal processing blocks
SC circuits as charge processors - 1
(a) Elementary charge mirror and (b) Basic SC signal processing blocks
CMOS Analog Design Using All-Region MOSFET Modeling

21. CMOS Analog Design Using All-Region MOSFET Modeling
SC circuits as charge processors - 2
Third-order SC filter
CMOS Analog Design Using All-Region MOSFET Modeling

22. CMOS Analog Design Using All-Region MOSFET Modeling
SC circuits as charge processors - 3
Signal-flow graph of the third-order SC filter
CMOS Analog Design Using All-Region MOSFET Modeling

23. CMOS Analog Design Using All-Region MOSFET Modeling
SC circuits as charge processors - 4
Measured output waveforms at (a) an intermediate node and (b) output node of an SC filter implemented with nonlinear capacitors, with the exception of the linear input and output capacitors
CMOS Analog Design Using All-Region MOSFET Modeling