1 ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network Prof. Hsien-Hsin Sean Lee School of ECE Georgia Institute of Technology.

Slides:



Advertisements
Similar presentations
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.
Advertisements

Digital CMOS Logic Circuits
CT455: Computer Organization Logic gate
L14: Boolean Logic and Basic Gates
CSET 4650 Field Programmable Logic Devices
ECE2030 Introduction to Computer Engineering Lecture 9: Combinational Logic, Mixed Logic Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering.
Logic Design Fundamentals - 1 Lecture L1.1. Logic Design Fundamentals - 1 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 13 CMOS Digital Logic Circuits.
S. RossEECS 40 Spring 2003 Lecture 22 Inside the CMOS inverter, no I D current flows through transistors when input is logic 1 or logic 0, because the.
ECE C03 Lecture 41 Lecture 4 Combinational Logic Implementation Technologies Prith Banerjee ECE C03 Advanced Digital Design Spring 1998.
EE 4271 VLSI Design, Fall 2011 CMOS Combinational Gate.
EE365 Adv. Digital Circuit Design Clarkson University Lecture #4
Lecture 21 Today we will Revisit the CMOS inverter, concentrating on logic 0 and logic 1 inputs Come up with an easy model for MOS transistors involved.
Lecture #24 Gates to circuits
S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 20: Combinational Circuit Design (2/3) Prof. Sherief Reda Division of Engineering,
Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley.
Lecture #25 Timing issues
S. Reda VLSI Design Design and Implementation of VLSI Systems (EN1600) lecture09 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008.
ECE 331 – Digital System Design Basic Logic Functions, Truth Tables, and Standard Logic Gates.
Digital CMOS Logic Circuits
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 5 Dr. Shi Dept. of Electrical and Computer Engineering.
Field-Effect Transistors 1.Understand MOSFET operation. 2. Understand the basic operation of CMOS logic gates. 3. Make use of p-fet and n-fet for logic.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 18: Static Combinational Circuit Design (2/2) Prof. Sherief Reda Division.
ECE2030 Introduction to Computer Engineering Lecture 3: Switches and CMOS Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia.
Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Combinational logic functions. n Static complementary logic gate structures.
ECE 331 – Digital System Design Transistor Technologies, and Realizing Logic Gates using CMOS Circuits (Lecture #23)
UNIT-8 LOGIC GATES.
EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009
MOS Transistors The gate material of Metal Oxide Semiconductor Field Effect Transistors was original made of metal hence the name. Present day devices’
Chapter 3 Digital Logic Structures. 3-2 Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2000):
NOCTI Review Lesson 4 Objectives:
LOGIC GATES & TRUTH TABLE – Digital Circuit 1 Choopan Rattanapoka.
Complementary CMOS Logic Style Construction (cont.) Digital Integrated Circuits© Prentice Hall 1995 Introduction.
Complementary CMOS Logic Style Construction (cont.)
Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-1 Lecture 14 CMOS Logic Gates Feb. 5, 2003.
Chapter 1 Combinational CMOS Logic Circuits Lecture # 4 Pass Transistors and Transmission Gates.
Logic Gates Shashidhara H S Dept. of ISE MSRIT. Basic Logic Design and Boolean Algebra GATES = basic digital building blocks which correspond to and perform.
3. Logic Gate 3.1 Introduction static, fully complementary CMOS psudo-nMOS, domino logic 3.2 Combinational Logic Functions combinational logic ---- specification.
Week 6: Gates and Circuits: PART I READING: Chapter 4.
ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Static CMOS Logic ECE442: Digital Electronics.
Sneha.  Gates Gates  Characteristics of gates Characteristics of gates  Basic Gates Basic Gates  AND Gate AND Gate  OR gate OR gate  NOT gate NOT.
ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech.
EE210 Digital Electronics Class Lecture 9 April 08, 2009.
Logic Gates. The Inverter The inverter (NOT circuit) performs the operation called inversion or complementation. Standard logic symbols: 1 1 input output.
Computer Organization and Design Transistors and all that… a brief overview Montek Singh Oct 12, 2015 Lecture 9 1.
 Seattle Pacific University EE Logic System DesignNMOS-CMOS-1 Voltage-controlled Switches In order to build circuits that implement logic, we need.
1. Digital cmos.2 10/15 Figure 10.1 Digital IC technologies and logic-circuit families. Digital IC Technologies CMOS & Pass Transistor Logic dominate.
1 Contents Reviewed Rabaey CH 3, 4, and 6. 2 Physical Structure of MOS Transistors: the NMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
ECE2030 Introduction to Computer Engineering Lecture 6: Canonical (Standard) Forms Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering.
Boolean Algebra and Logic Gates
Lecture 20 Today we will Look at why our NMOS and PMOS inverters might not be the best inverter designs Introduce the CMOS inverter Analyze how the CMOS.
Static CMOS Logic Seating chart updates
EECS 270: Inside Logic Gates (CMOS)
ECE2030 Introduction to Computer Engineering Lecture 5: Boolean Algebra Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia.
Solid-State Devices & Circuits
CMOS Logic Gates. NMOS transistor acts as a switch 2 When gate voltage is 0 V No channel is formed current does not flow easily “open switch” When gate.
Introduction to CMOS Transistor and Transistor Fundamental
ECE DIGITAL LOGIC LECTURE 5: BINARY LOGIC AND DIGITAL LOGIC GATES Assistant Prof. Fareena Saqib Florida Institute of Technology Fall 2016, 01/28/2016.
Computer Organization and Design Transistors & Logic - II Montek Singh Mon, Mar 14, 2011 Lecture 9.
Computer Organization and Design Transistors & Logic - I Montek Singh Wed, Oct 14, 2013 Lecture 9 1.
Computer Organization and Design Transistors & Logic - II Montek Singh Wed, Oct 17, 2012 Lecture 11.
COMP541 Transistors and all that… a brief overview
ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network
Logic Gates.
Digital Signals Digital Signals have two basic states:
Design of Combinational Logic
Prof. Hsien-Hsin Sean Lee
Logic Gates.
COMBINATIONAL LOGIC DESIGN
COMP541 Transistors and all that… a brief overview
Presentation transcript:

1 ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network Prof. Hsien-Hsin Sean Lee School of ECE Georgia Institute of Technology

H.-H. S. Lee 2 CMOS Inverter Connect the following terminals of a PMOS and an NMOS Gates Drains V in V out V dd Gnd V out V in V in = HIGH V out = LOW (Gnd) ON OFF V dd Gnd V out V in V in = LOW V out = HIGH (V dd ) ON OFF V dd PMOS Ground NMOS

H.-H. S. Lee 3 CMOS Voltage Transfer Characteristics V dd Gnd V in V out PMOS NMOS OFF: V_GateToSource < V_Threshold LINEAR (or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSource Note that in the CMOS Inverter  V_GateToSource = V_in

H.-H. S. Lee 4 Pull-Up and Pull-Down Network CMOS network consists of a Pull- UP Network (PUN) and a Pull- Down Network (PDN) PUN consists of a set of PMOS transistors PDN consists of a set of NMOS transistors PUN and PDN implementations are complimentary to each other PMOS  NOMS Series topology  Parallel topology …. I0I0 I1I1 I n-1 OUPTUT V dd PUN Gnd PDN

H.-H. S. Lee 5 PUN/PDN of a CMOS Inverter AB 01 1Z AB 0Z 10 AB Pull-Up Network Pull-Down Network Combined CMOS Network V dd A Gnd B CMOS Inverter

H.-H. S. Lee 6 Gate Symbol of a CMOS Inverter V dd A Gnd B CMOS Inverter AB B = Ā

H.-H. S. Lee 7 PUN/PDN of a NAND Gate ABC Z ABC 00Z 01Z 10Z 110 Pull-Up Network Pull-Down Network V dd A B A B C

H.-H. S. Lee 8 PUN/PDN of a NAND Gate ABC Z ABC 00Z 01Z 10Z 110 ABC Pull-Up Network Pull-Down Network Combined CMOS Network V dd A B A B C

H.-H. S. Lee 9 NAND Gate Symbol ABC V dd A B A B C A B C Truth Table

H.-H. S. Lee 10 PUN/PDN of a NOR Gate ABC Z 10Z 11Z ABC 00Z Pull-Up Network Pull-Down Network V dd A C B A B

H.-H. S. Lee 11 PUN/PDN of a NOR Gate ABC Z 10Z 11Z ABC 00Z ABC Pull-Up Network Pull-Down Network Combined CMOS Network A C B A B V dd

H.-H. S. Lee 12 NOR Gate Symbol ABC A B C Truth Table A C B A B V dd

H.-H. S. Lee 13 How about an AND gate V dd A B A Gnd C NAND Inverter B C = A B A B C

H.-H. S. Lee 14 An OR Gate A B A B V dd Gnd C Inverter NOR A B C

H.-H. S. Lee 15 What’s the Function of the following CMOS Network? V dd C ABC 00Z Z ABC Z 10Z 110 ABC Pull-Up Network Pull-Down Network Combined CMOS Network XOR Function = XOR

H.-H. S. Lee 16 Yet Another XOR CMOS Network V dd C ABC 00Z Z ABC Z 10Z 110 ABC Pull-Up Network Pull-Down Network Combined CMOS Network XOR Function = XOR

H.-H. S. Lee 17 Exclusive-OR (XOR) Gate V dd C ABC A B C Truth Table

H.-H. S. Lee 18 XNOR How about XNOR Gate ABC A B C Truth Table How do we draw the corresponding CMOS network given a Boolean equation?

H.-H. S. Lee 19 XNOR How about XNOR Gate ABC A B C Truth Table V dd C XOR Inverter

H.-H. S. Lee 20 A Systematic Approach Each variable in the given Boolean eqn corresponds to a PMOS transistor in PUN and an NMOS transistor in PDN PUN Draw PUN using PMOS based on the Boolean eqn ANDseries AND operation drawn in series ORparallel OR operation drawn in parallel variable Invert each variable of the Boolean eqn as the gate input for each PMOS in the PUN PDN Draw PDN using NMOS in complementary form Parallel (PUN) to series (PDN) Series (PUN) to parallel (PDN) Label with the same inputs of PUN Label the output

H.-H. S. Lee 21 Example 1 In series In parallel Vdd (1) Draw the Pull-Up Network

H.-H. S. Lee 22 Example 1 In series In parallel Vdd (2) Assign the complemented input A C B

H.-H. S. Lee 23 Example 1 In series In parallel Vdd (3) Draw the Pull-Down Network in the complementary form A C B A C

H.-H. S. Lee 24 Example 1 In series In parallel Vdd (3) Draw the Pull-Down Network in the complementary form A C B A CB

H.-H. S. Lee 25 Example 1 In series In parallel Vdd Label the output F A C B A CB F

H.-H. S. Lee 26 Example 1 In series In parallel Vdd A C B A CB F ABCF Truth Table

H.-H. S. Lee 27 An Alternative for XNOR Gate ABC A B C Truth Table V dd C

H.-H. S. Lee 28 Example 3 Start from the innermost term A B D AC A D

H.-H. S. Lee 29 Example 3 Start from the innermost term A B D AC A D A C

H.-H. S. Lee 30 Example 3 Start from the innermost term A B D AC A D A C B

H.-H. S. Lee 31 Example 3 Start from the innermost term A B D AC A D A C B Vdd F Pull-Up Network Pull-Down Network

H.-H. S. Lee 32 Example 4 Start from the innermost term A B D A C A D A C B Vdd F E D E D Pull-Down Network Pull-Up Network

H.-H. S. Lee 33 Another Example How ??