University of Maryland at College Park Smart Dust Digital Processing, 1 Digital Processing Platform Low power design and implementation of computation associated with protocols and fusion algorithms Low power micro-controller Small size for compact integration Enables adaptation of node behavior with changing requirements, environmental characteristics, and network state Enables experimentation with different algorithms and protocols Enables use of energy saving processor modes and associated operating system functionality Development of streamlined software implementations Highly memory-constrained software implementations are required due to size and energy constraints Must handle streaming nature of input data Leverage our previous work in synthesis of memory-efficient embedded software implementations Employ formal programming models, and apply graph-theoretic analysis and optimization of program structure Explore migration into ASIC or 3D-integrated system

University of Maryland at College Park Smart Dust Digital Processing, 2 Example of Software Structure Low power sleep mode Periodic wake-up Check for new data No new data Extract data Fuse with prior data Need to update neighbors? No Broadcast new data Yes Receiver Sensor Transmitter

University of Maryland at College Park Smart Dust Digital Processing, 3 Protocol Set-up and System Configuration Handshaking Source channel coding Integrate with transceiver to establish PLL timing Establish error correction coding Establish low-complexity decoding Assign transmission power Assign processing tasks to network nodes

University of Maryland at College Park Smart Dust Digital Processing, 4 System-level Optimization Example: Task Assignment Algorithms Need to balance communication and computation throughout the network Develop models of power consumption in network nodes and communication links Develop task graph models of overall network functionality Develop algorithms to embed task graph algorithm specifications into the network Assign processing tasks to network nodes Turn off idle nodes Large design space Explore evolutionary algorithms to optimize task graph embeddings

University of Maryland at College Park Smart Dust Digital Processing, 5 Evolutionary Algorithms Phenotype space (Original search space) P(t+1) P(t) Selection Genotype space (Genetic representation) G(t+1) G(t) Genetic operators Decoding function

University of Maryland at College Park Smart Dust Digital Processing, 6 Digital Design Summary Contributions Low power, memory-constrained implementation techniques Application-specific optimization of software and VLSI Integrated optimization of protocols and system configuration Selected Prior Work N. K. Bambha, S. S. Bhattacharyya, J. Teich, and E. Zitzler. Systematic integration of parameterized local search in evolutionary algorithms. IEEE Transactions on Evolutionary Computation. To appear. S. S. Bhattacharyya. Hardware/software co-synthesis of DSP systems. In Y. H. Hu, editor, Programmable Digital Signal Processors: Architecture, Programming, and Applications, pages Marcel Dekker, Inc., P. K. Murthy and S. S. Bhattacharyya. Shared buffer implementations of signal processing systems using lifetime analysis techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(2): , February S. S. Bhattacharyya, R. Leupers, and P. Marwedel. Software synthesis and code generation for DSP. IEEE Transactions on Circuits and Systems --- II: Analog and Digital Signal Processing, 47(9): , September 2000.