1. MAPLD 2005/254C. Papachristou 1 Reconfigurable and Evolvable Hardware Fabric Chris Papachristou, Frank Wolff Robert Ewing Electrical Engineering & Computer Science AFRL/AFTA, Bldg 620 Case Western Reserve University Wright Patterson Cleveland, Ohio 44106 WPAFB, OH 45433 September 7, 2005

2. MAPLD 2005/254C. Papachristou 2 A novel reconfigurable processor for high data rate agile communications Features - Reconfigurability & adaptability, - Low power, system-on-chip technology, - Real time, robust performance, - Fault tolerance, - Self-healing. Platform: autonomous sensor or unit being a typical node in space Project Overview

3. MAPLD 2005/254C. Papachristou 3 Concept: The Big Picture

4. MAPLD 2005/254C. Papachristou 4 Background Ability of a device to change its internal structure, functionality, and behavior, either on command, or autonomously. Reconfigurability Classes Static Configuration: performed while device is off line. Dynamic Configuration : device is on-line, "on the fly". Self Reconfiguration : performed autonomously by device. Evolution type: Self Reconfiguration with adaptation such as replication and growth, "bio-inspired".... Reconfigurability

5. MAPLD 2005/254C. Papachristou 5 Technology Assessment Advantages over competing FPGA and DSP processors: Flexibility: ability for self-reconfiguration Granularity: ability to scale for variable bit-length operations Cost: simpler upgrading of protocols, algorithms, code schemes Fault Tolerance: ability for self repair and self healing from SEUs Low Power: efficient energy consumption through configuration

6. MAPLD 2005/254C. Papachristou 6 Enhancements to Space Technology Communication Requirements in Missions Rapid adaptation of onboard systems to changing environments Dynamic communications links: - self adaptable bandwidth to meet changing throughput requirements - self managing channel capacity Passive communication to reduce power Communication Protocol adaptation: - adapt to changing communication protocols for each situation Reconfigurable Hardware: enabling technology to meet these requirements.

7. MAPLD 2005/254C. Papachristou 7 Sensor Web Scenario Comm Tradeoffs Bandwidth = Buffer/Latency Data Rate, Protocol, ErrorBit Rate.

8. MAPLD 2005/254C. Papachristou 8 Approach Architecture: reconfigurable at four Layers: Layer 4: the Adaptation Manager. Layer 3: the Real-Time Operating System RTOS. Layer 2: the Embedded Processors and Memory. Layer 1: the Reconfigurable Hardware Fabric.

9. MAPLD 2005/254C. Papachristou 9 Architecture: Non Traditional Reconfigurable

10. MAPLD 2005/254C. Papachristou 10 Occurs at several levels: (a) Selection of application modules by the Adaptation Manager. (b) Mapping of modules into the hardware fabric or the embedded processors, depending on performance requirements. (c) Configuration of the hardware fabric and the embedded processor to meet performance and data delivery requirements. The reconfigurable hardware is essential for mapping of wireless communications algorithms such as : IR filtering, multichannel CDMA, complex encoding, advanced imaging. Reconfiguration Strategy

11. MAPLD 2005/254C. Papachristou 11 Self Adaptation - Dynamic Configuration

12. MAPLD 2005/254C. Papachristou 12 Reconfigurable Fabric

13. MAPLD 2005/254C. Papachristou 13 Reconfigurable Tile

14. MAPLD 2005/254C. Papachristou 14 Core Switch Matrix

15. MAPLD 2005/254C. Papachristou 15 Double Buffer Configuration Switch Cell

16. MAPLD 2005/254C. Papachristou 16 is capable of on-line adaptation by autonomously reconfiguring its architecture either through software or by directly morphing the hardware. The key idea is to achieve evolution in the hardware by evolving configuration candidates via a neural network and testing them for fitness. A best fit configuration will morph the hardware to best responding to a particular input stimulus. Evolvable Hardware

17. MAPLD 2005/254C. Papachristou 17 Evolvable Platform

18. MAPLD 2005/254C. Papachristou 18 Operation mode: NN generates configuration code Training mode: NN incrementally evolves configurations by training itself on input stimuli as well as configuration data that are recurrently applied after being improved by genetic operations. Other evolution modes e.g. self-diagnosis and self repair are also feasible. Evolution modes:

19. MAPLD 2005/254C. Papachristou 19 During training, candidate configurations are selected from a population via genetic operations. Training continues until a candidate passes a fitness test depending on responses from the hardware fabric. Training may start on command or autonomously, in new environment, new functions or upgrading for better performance. A major aspect of this scheme is to design a robust training mechanism for configuration evolution of the dynamic hardware fabric. Training

20. MAPLD 2005/254C. Papachristou 20 Evolvable Hardware Training

21. MAPLD 2005/254C. Papachristou 21 Configuration Tools Binding Configurator Algorithm Data Flow Arch Resource Netlist Connectivity Bindings Architecture Mapper Synthesis tools

22. MAPLD 2005/254C. Papachristou 22 Configuration Tools (Cont.) Synthesis: Data Flow transormation of the application into a resource graph. Binding: allocation of resources into configurable modules, This involves functional, local memories and interconnect modules. Configuration Core: compact description of the mapping -- in space and time Loading the configuration matrix into Buffere FIFOs to employ the mapping.

23. MAPLD 2005/254C. Papachristou 23 Results on Some Benches

24. MAPLD 2005/254C. Papachristou 24 Proof of Concept For proof of concept, we will employ advanced FPGA boards from Xilinx and Altera, as well as CAD tools that we have obtained from commercial vendors. We will develop an advanced prototyping environment based on these tools and software. We will implement by emulation our proposed reconfigurable hardware on these boards, without actual chip design. Emulation and prototyping is quite feasible.