WISDOM WP6 Manufacturability, Scalability and Functionality Study Start M0, End M35 WP leader is CIP Objectives –Assessment of manufacturability of the sub-systems used in the optical firewall –Establishing the optimum balance between optical and electronic processing for the firewall function –Platform scalability & functionality

Manufacturability (Optics) Simplified manufacture of components –New daughterboard fabrication process using a single photolithographic step to define all critical features Further development of a self-correcting daughterboard design started – patent in preparation –Replaced milling of recesses individually with wafer scale ICP etching Investment in manufacturing equipment –Spray coater for applying photoresist over severe topology –Flip chip bonder for back end assembly

Daughterboards

Optimum Balance Optimum balance between optics & electronics –Gaining visibility of costs of present electronic systems (Endace system >$100k for 40G unit as at 2007) –Developing cost model for integrated pattern matching circuit –Indicative cost of control electronics being established –Need to establish cost/benefit of optics and what it would replace in the electronics to get a more realistic view of opportunity

Scalability - Optics Scalability – optics –Higher delta waveguides to reduce bend radii Good for reducing footprint of time delay structures Electrical lines become size limit below ~ 1mm bend radius. Size reduction through attention to other factors, eg TO switches, InP device array size, daughterboard size 5mm bend radius Chip size 48.5x10mm 3ps delay 3mm bend radius Chip size 40x10mm 1mm bend radius Chip size 39x10mm

Multiple pattern recognition Inverting input Non- inverting input 1 2 Clock probes Repeated data m-1 m Output m-1 Output m Interleaved targets T 1 //T 2 For m targets, number of gates = m+1 number of slow switches = m Slow (~1ns) 1x2 switches XNOR function 2 WDM Demux (n+1)T Output 1 Output 2 WDM Demux WDM Mux AND gates

Functionality Developing additional functional elements on hybrid platform. Passive circuitry now ‘standard’ Key element for pattern matching circuit is inclusion of thin film filter into the waveguides Working towards defining standards for interfaces to make platform more widely applicable

Next Generation Threats - Landscape

Desirable Security Platform Features High performance and lower costs Multiple 10Gb/s backplane chassis in the market today Support virtualisation Decreases cost per licence – Low management cost Reduction of deployment expenses – Hardware cost benefits Environmental (Less power & low heating emission) High availability (occupy less space)

Plans for Y3 Refine device designs to simplify manufacture and establish high device yield (this is the primary driver for cost of manufacture) Establish key aspects of scalability in terms of speed of operation of the pattern matching circuit, and the practical number of gates per circuit (this will be a moving target) Establish the scalability of the pattern matching approach in terms of practical implementation of security rules. That is, find out what is the most efficient way of implementing the security rules with the optics and whether it is possible to have scaling rates of >1 for rules per circuit