12/10/01 - Cecilia Gerber UIC Slide 1 Testing Card specifications l Will be used in the Run2b SASEQ-based test stands  40+16+15 needed. Build 75, two.

Slides:



Advertisements
Similar presentations
Twisted Pair Cable Dense assembly (OD 5-7 mm) with –Twisted pairs : total 21; 44-pin mm dual row Omnetics connector differential signals single-ended.
Advertisements

M. Noy. Imperial College London Calice MAPS Adapter Card Review M. Noy 26 th June 2007.
Bagby L0 Workshop L0 Infrastructure  Mapping  Installations u Horseshoe Area s Adapter Card u Cathedral s Low Voltage Fuse Panel u Platform s.
ESODAC Study for a new ESO Detector Array Controller.
STARLight PDR 3 Oct ‘01I.1 Miller STARLight Control Module Design Ryan Miller STARLight Electrical Engineer (734)
04/02/2004 az Outer Tracker Distribution Boxes 1 EFNI H K Outer Tracker Distribution Boxes Ad Berkien Tom Sluijk Albert Zwart.
20 Feb 2002Readout electronics1 Status of the readout design Paul Dauncey Imperial College Outline: Basic concept Features of proposal VFE interface issues.
July 10, 2008 PHENIX RPC review C.Y. Chi 1 RPC Front End Electronics On chamber discriminator  The strips  The CMS discriminator chips  The discriminator.
PALM-3000 P3K FPDP Carrier Board Review Dean Palmer Building 318, Room 125 November 10, :00 am – 12:00 pm.
RPC Electronics Overall system diagram –At detector –Inside racks Current status –Discriminator board –TDC board –Remaining task.
LarTPC Electronics Meeting Current Work at MSU Fermilab Dan Edmunds 23-February-2010.
DAQ for KEK beam test M.Yoshida (Osaka Univ.). Components VLPC readout –Stand Alone Sequencer (SASeq) Slow < 100Hz –Buffering VLPC data with VME interface.
CheckSystem 2.1 Portable Test Systems Page 1 April 2011.
Measuring Leakage Current on Singles and Ladders P. Riedler and S. Ceresa, August 2005 Sensor Chip Manipulator Needle for sensor back side contact Probe-card.
ZTF Interconnecting Scheme Stephen Kaye
Leo Greiner IPHC testing Sensor and infrastructure testing at LBL. Capabilities and Plan.
Ageing … Eric Kajfasz (CPPMarseille) D0 Workshop, Beaune, June 17, 2003 DØSMT.
Main Board Status MB2 v1 for FATALIC & QIE 10/06/2015Roméo BONNEFOY - LPC Clermont1 Roméo BONNEFOY François Vazeille LPC Clermont-Ferrand.
LKr Calorimeter Control and monitoring R. Fantechi 19/02/2010 R. Fantechi.
Figure 1: ICD Single Channel Block Diagram Schematic PMT High Voltage Supply (see Figure 4 & 4a) LED Pulser PMT Calibration (see Figure 6) ICD Scintillator.
LNL 1 SLOW CONTROLS FOR CMS DRIFT TUBE CHAMBERS M. Bellato, L. Castellani INFN Sezione di Padova.
January 22, 1999SciFi L1 Trigger Review 1 Analog Hardware Front-end Board (CTT_FE) –Transmit (and split) the VLPC signal to the Multi-chip Modules –Discriminate.
Mapping for Silicon Run IIb L. Bagby, A. Nomerotski, E. von Toerne December 2002
HBD FEM the block diagram preamp – FEM cable Status Stuffs need to be decided….
HBD FEM Overall block diagram Individual building blocks Outlook ¼ detector build.
Bagby, Foglesong General Silicon Meeting Run IIb LVPS Status  Design Goals  Key Issues  System Diagrams  Prototype – 1%  Plans.
1 Chap. 3 Interface. 2 Interface  Physical connection between node and transceiver  Network interface card (NIC)  Physical connection between transceivers.
Oct 29, 2001 Ron Sidwell 1 Purple Card. Oct 29, 2001 Ron Sidwell 2 Purple Card Spec Two channels per printed circuit board Size ~20 sq. in. or best effort,
Acquisition Crate Design BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’ 26 August
Status of NA62 straw electronics Webs Covers Services Readout.
Andrei Nomerotski, Fermilab Silicon Electronics & Readout Silicon Electronics & Readout Andrei Nomerotski, D0/Fermilab April , Temple Review Overview.
FE-I4 Test Setup Hardware Needs: Boards & Interfaces March 1 st 2010, Marlon Barbero.
L0 Technical Readiness Review-Electronics Installation Linda Bagby L0 Electronics Installation  System Electronics Overview u Low Voltage s Filter.
Test Tube Activities at Ohio State (8/5/03) Two (very useful) sub-group meetings after last weekly meeting –Mechanics (Bill, Lu, Mark, Jim, Charlie, Klaus)
Towards a final design of LAV front-end M. Raggi, T. Spadaro, P. Valente & G. Corradi, C. Paglia, D. Tagnani.
Twisted Pair Cable A.Nomerotski 12/12/02  Dense assembly (OD 5-7 mm) with u Twisted pairs : total 21; 44-pin mm dual row Omnetics connector s differential.
OD HV Upgrade Hans Berns Jeff Wilkes U. of Washington 10/14/01.
AHCAL Physics Prototype. The Electronics Part Mathias Reinecke for the AHCAL developers DESY, March 2nd, 2010.
Director’s Review of RunIIb Dzero Upgrade Installation Linda Bagby L0 Electronics Installation  System Electronics Overview u Low Voltage u High.
Front End Board (16 channels) Superlayer Cross Section Frontend Enclosure HV cap board HV cap Board Signals from chamber wires go to HV cap board to be.
FEC electronicsRD-51 mini week, CERN, Sept Towards the scalable readout system: FEC electronics for APV25, AFTER and Timepix J.
Electronics: Junction Cards, Adapter Card, Purple Card, …. Ron Sidwell, K. Harder, T. Sobering, R. Taylor, E. VonToerne, Kansas State U.
GLAST LAT ProjectMarch 24, C Tracker Peer Review, WBS GLAST Large Area Telescope: Tracker Subsystem WBS C: Electronics Module Testing.
Connector Differential Receiver 8 Channels 65 MHz 12 bits ADC FPGA Receive/buffer ADC data Format triggered Events Generate L1 Primitives Receive timing.
12 September 2006Silicon Strip Detector Readout Module J. Hoffmann SIDEREM SIlicon Strip DEtector REadout Module.
9/18/2003Safety Review Electronics Electronics design LV, HV power supply Fusing Heat.
12/17/01 Ron Sidwell 1 Run2b Datapath 17 Dec Update Bill Reay, Ron Sidwell, Noel Stanton, Russell Taylor, Kansas State University.
11 October 2002Paul Dauncey - CDR Introduction1 CDR Introduction and Overview Paul Dauncey Imperial College London.
Ron Sidwell 1 L0 Datapath Ron Sidwell, Noel Stanton, Russ Taylor The Kansas State University.
Dzero Collaboration Meeting, Sept. 14, M. DemarteauEric Flattum - Fermilab 1 Slide 1 Alice Bean Fermilab/University of Kansas for the D0 Run2b silicon.
New digital readout of HFRAMDON neutron counters Proposal Version 2.
Drift Chamber Review Jefferson Lab 6-8 March 2007 CLAS12 Drift Chamber Electronics R. Chris Cuevas Group Leader -- Fast Electronics Jefferson Lab Physics.
Week 22: Schematic Week 23-Week 27: Routing Gerber files have been available since 9th July 1st prototype: – PCB manufacturer: supervised by KIT – Cabling:
Martin van Beuzekom, Jan Buytaert, Lars Eklund Opto & Power Board (OPB) Summary of the functionality of the opto & power board.
LHCb Outer Tracker Electronics 40MHz Upgrade
Setup for automated measurements (parametrization) of ASD2 chip
Vinculum II Development Modules
on behalf of the AGH and UJ PANDA groups
ECAL Front-end development
BI-day 2014, The SEM-grid renovation project Michel Duraffourg
HPS Motherboard Electronic Design
S12X Full-Emulator: Pictures of the Emulator Hardware
PRODUCTION BOARDS TESTING
HCAL HV splice box.
NA61 - Single Computer DAQ !
PRODUCTION BOARDS TESTING
RPC Front End Electronics
RPC Electronics Overall system diagram Current status At detector
TOF & BB FEE Safety Review
Presentation transcript:

12/10/01 - Cecilia Gerber UIC Slide 1 Testing Card specifications l Will be used in the Run2b SASEQ-based test stands  needed. Build 75, two channels each. l Will replace the IB and the adapter card  Connects to SASEQ (50 conductor cable)  Takes two jumper cables (2 AVX connectors)  Will also have twisted pair cable connectors. l Should fit in the cool&dry box with the detectors  6U size or smaller l Functionally of the purple card is similar to the active adapter card, but with additional functions indicated in purple. C. Gerber (UIC) Silicon Electrical Meeting, 1/14/02 A. Nomerotski 1/15/02

12/10/01 - Cecilia Gerber UIC Slide 2 New Test Card

12/10/01 - Cecilia Gerber UIC Slide 3 Testing Card specifications l two channels per printed circuit board l size ~20 sq. in. or best effort l voltage regulation of SVX4 power (and possibly board power if needed) l SVX4 voltage (8-pin header) controlled by HDI enable/disable from SASEQ l Output for temperature monitoring (and voltage monitoring?), options for monitors:  VMIC Scanning ADC (requires VME)  NWU microprocessor connected to PC via serial link ?  voltmeter

12/10/01 - Cecilia Gerber UIC Slide 4 Specifications (cont.) l HV (silicon bias) supplied via a LEMO connector, and controlled by HDI enable/disable from the SASEQ l CAL-SR LEMO connector (two connectors) l fuses (resettable if feasible) on SVX4 power, and board power l Dvalid delay provision; SIP l clock conversion from TTL to low-voltage differential l one input 50-conductor connector from SASEQ

12/10/01 - Cecilia Gerber UIC Slide 5 Specifications (cont.) l Target date: July '02 for working prototype.  set on specs by 1/31/01  First iteration (2 stuffed boards) by May 02  working boards at Fermilab on 7/1/02 l Probable cost:  ~$25K, includes production of prototypes and ONE turnaround  + $5-7K if second turnaround is needed.  two channel interface card cost was $40-45K (for reference)