Chapter 8. Sequential machine

Sequential machine M = ( I, O, S, , ) I : set of input O : set of output S : set of states  (state transition) : I  S  S for i  I, s  S  (i,s)  S’ : Output function, if : I  S  O “Mealy machine” : S  O “Moore machine” Serial Adder x2x2 x1x1 Z Combinational circuit Input X Output Z Next state SCurrent state S M M

S1S2 SnS1S2 Sn I 1 I 2 I n I S S i /O j Next state/output S1S2 SnS1S2 Sn I 1 I 2 I n I S SiSi Output OjOj Mealy machineMoore machine Moore machine  Mealy machine Z I S 1/0 2/1 4/0 3/1 4/0 3/1 2/1 1/ I S  Mealy machine  Moore machine 1/0 2/1 4/1 3/0 4/1 1/0 2/1 3/ I S Z ’ ’ 0 1 I S  State equivalence and machine minimization. Two finite state machine m 1 and m 2 are equivalent iff for any state of m 1, say S 1, there is some state of m 2, say S 2, such that starting with m 1 in state s 1 and m 2 in state S 2 and applying say sequence of inputs, results in an identical sequence of outputs from m 1 and m 2. In such case, S 1 and S 2 are called equivalent states.

Simplification of completely specified machines The sets of equivalent states of a machine from a portion of the states of the machine. The minimal machine corresponding to this machine will have a state for each equivalence class of the original machine. The states, S 1 and S 2, are k-equivalent if for any input sequence of length  k, the same output seq. is produced regardless of whether S 1 and S 2 were the initial state. Two states which are not k-equivalent, are called k-distinguishable. P 1 : partition imposed by grouping states whose outputs agree for any input sequence length by 1. Compute P i for i>1 such that two states S i and S k are in the same block of P i (i.e., are i-equivalent) iff S i and S k are (i-1)-equivalent (i.e., in the common block of P i-1 ) and for each input, the next states of S i & S k are (i-1)-equivalent.(i.e., are in the common block of P i-1 ) A/0 B/0 A/0 C/0 A/0 D/0 A/0 E/1 A/0 E/1 ABCDEABCDE 0 1 I S P k : partition imposed by grouping states whose outputs agree for any input sequence length of k. We can say, D & E are equivalent state. (Produce the same output) (transform)

 /0  /0  /0  /0  /0  /0  /0  /1  0 1 I S  reduced machine. We can say, minimal machine. We can reduced state table. E/0 D/1 F/0 D/0 E/0 B/1 F/0 B/0 C/0 F/1 B/0 C/0 ABCDEFABCDEF 0 1 I S (Same outputs) (Same outputs & same state) Simplification of incompletely specified machines Two states, S i and S j, a machine M are compatible iff for every input sequence applicable to both S i and S j, the same output sequence will be produced whenever both outputs are specified, regardless or whether S i and S j is the initial state. (outputs are not conflicting) While the equivalence partition consists of disjoint blocks, the subsets of compatible may be overlapping.

Example) 3/0 – 2/– – 4/0 6/– 5/1 – –/0 – 1/1 – 1/– – 6/– 4/– 5/– 6/– I 1 I 2 I 3 S 1- compatible  (different output) (1,3), (2,4) 2- compatible (1,5) 3- compatible (3,5), (4,6) 4- compatible (1,3) (already incompatible) Compatible pairs of states (1,2) (1,3) (1,4) (1,5) (1,6) (2,3) (2,4) (2,5) (2,6) (3,4) (3,5) (3,6) (4,5) (4,6) (5,6) Maximal Compatible Set (1,2,6) (1,4) (2,3,6) (2,5,6) (3,4) (4,5) Set of maximal compatible : set of compatible states (i.e., a compatibility class) which cannot be contained in any larger compatibility class.

We can find (from maximal compatible set) Lower bound required by the reduced machine  3 (to cover all states) (eg – {1,2,6},{3,4},{4,5}: the min # of maximum compatibles which cover all states) Upper bound : min (# of maximum compatible, # of original state)  6 (previous example) Suppose & pick (1,2,6) (2,3,6) (4,5) cabcba (2,3,6) (4,5) (1,2,6)(4,5) (1,4) Require another state  we can’t find 3 state machine.  try another possible case or try find 4 state machine. Suppose & pick (1,2,6)   (3,4)   (4,5)   abcabcabc (3,4) (4,5) (1,2,6) (4,5) (1,2,6)(1,2,6) (1,2,6) (1,2,6)

Reduced machine (only 3 state = lower bound)  minimum state machine  /0  /0  /–  /1  /1 –/0  /–  /1  /–  a b c Cover : every state of the original machine must be included Closed : For any compatibility class and any input, the next state of all states in this class, must also be in a common compatibility class used as a state of the reduced machine. – – – E/1 A/1 D/1 – A/– D/0 – B/1 F/– A/– B/0 – – E/– B/1 C/0 F/– –/1 A/0 – – ABCDEFABCDEF I4I4 I3 I3 I2I2 I1I1 S 1- compatible (A,C), (C,D), (B,F), (C,E) 2- compatible (A,D), (E,F) 3- compatible (B,C), (E,F) 4- compatible Compatible pairs (A,B) (A,E) (A,F) (B,D) (B,E) (C,F) (D,E) (D,F) maximum compatibility class (A,B,E), (A,F), (B,D,E), (C,F), (D,F)

Number of states in minimal machine lower bound : 3 upper bound : 5 We have to pick (C,F) (C,F)  (D,F)  (A,B,E) If we pick (C,F) then (D,F) will be another, then to make a 3-state machine. We have to choose(A,B,E) (C,F) (D,F) – (A,B,E) (D,F) (D,F)(A,B,E) (A,B,E) (C,F)or(D,F) (D,E) I4I4 I3I3 I2I2 I1I1 I4I4 I3I3 I2I2 I1I1 I4I4 I3I3 I2I2 I1I1 (C,F) (A,B,E) (A,B,E) (A,B,E) We can’t find a 3-states machine starting with (C,F) Next, only let C is a state. Start with C then (A,B,E), (D,F) – we can’t find a 3-state machine (A,F), (B,D,E) (B,D,E) I3I3 I2I2 I1I1 (A,F) (B,D,E) (A,B) We can’t find a 3-states machine  Add one more state If pick (C,F), (D,F), (A,B,E), (D,E)    

I4I4 I3I3 I2I2 I1I1 (D,E) (A,B,E) (D,E) (A,B,E) (A,B,E) or (A,B,E)  /1  /1  /1  /1  /0  /–  /1  /1  /1  /1  /0  /– –/1  /0  /0  /0  I4I4 I3 I3 I2I2 I1I1 S Reduced table Synchronous sequential machine – common clock Asynchronous sequential machine – non common clock What constitute input change Clock skew : different time between each circuit Flip-flop R S  ’’  ’’ R S clock R/S 0101 0  0 0  1 1  0 1  1 transitionoutput 0 – – 0 0101 Required input S R output transition

0 – 1 – – 1 – 0 0101 Required input J K output transition J/K flip-flop 101 Required input D output transition D flip-flop 101 Required input T output transition T flip-flop Synthesis of synchronous sequential circuits 1. From the specification of problem, from a state table (or a state diagram) 2. Minimize the machine 3. Select a state assignment and determine the type of memory elements 4. Drive output transition and output tables 5. Draw a circuit diagram even blocks of zero or odd blocks of one Sequential machine E D C B A 1/0 0/0 0/1 1/0 1/1 0/0 1/0 0/0 B: in a sum of zeros, seen an odd # of zeros C: in a sum of ones seen an odd # of ones D: in a sum of zeros seem am even # of zeros E: in a sum of zeros seen an even # of ones

B/0 C/0 D/0 C/1 B/0 E/0 B/0 C/0 B/0 C/1 ABCDEABCDE 0 1 I S Reduced   /0  /0  /0  /1  /0  /0  /0  /1  0 1 I S

x y 1 y 2 Output (Z) Z=y 1 y 2 x’+y 1 ’y 1 x Combinational Circuit x y Z M x y1y1 y2y2 y1y1 J1J1 K1K1 y2y2 J2J2 K2K2 Z Iterative networks: a cascade of identical circuits (or cells) Combinational Circuit Q x k x 2 x 1 M Z k Z 2 Z 1 yiyi YiYi Q x1x1 Z1Z1 Q x2x2 Z2Z2 Q Q xkxk ZkZk

Asynchronous Sequential circuit Combinational circuit I Z YiYi yiyi   Total state: next state equal to the present state. Stable state State table SiSi IjIj P.S. One stable state Primitive flow table assumption: Only one stable state per row, and outputs are specified only for stable state. bar l Prob. 11-9

Short bar just cleared B 2 and another under B 1 C J/1 DJ Long bar under B 2 and another bar under B 1 I/0I Short bar under B 2 and another bar under B 1 J H/0H Short bar passed both beams & nothing under B 1 G/1 JG Long bar under B 2 only and nothing under B 1 A F/0 IF Short bar under B 2 only G E/0 HE Long bar under both beams F D/0D Short bar between beams C/0 EC One bar is under B 1 C B/0 DB No bar under beams or between beams A/0 BA x 1 x 2 state Maximal compatible class (ABCI), (ABDFI), (CHJ), (DGI), (EG), (EH), (F,J) Best closed cover (ABCI), (DFI), (EG), (DHJ)   /0   /0  /0    /1   /0  /1   /0   /1   x1x2x1x2

State assignment in asynchronous sequential circuit Combinational circuit I Z Y1Y1 y1y1   YkYk ykyk Not common clock Race occurs anytime multiple state variables must change during a state transition Critical race : A race which may result in reaching an erroneous stable state (vs. Non critical race) The assignment of multiple vars must be such that the circuit will operate correctly even if different delays are associated with the secondary elements. BDCCBDCC DCDDDCDD AAADAAAD CCCCCCCC ABCDABCD x 1 x 2 y 1 y x 1 x 2 y 1 y 2 If x 1 x 2 =00 current state y 1 y 2 =00  y 1 y 2 =11(stable state) If x 1 x 2 =01 current state y 1 y 2 =11  y 1 y 2 =00 or 10

A  00 B  01 C  10 D  x 1 x 2 y 1 y 2 For valid state assignment, each transition is accomplished by change of secondary state 1. In which only one secondary variable change 2. In which a multiple change of secondary variables does not result in a critical race Multiple transition time state assignment            Same we can say ( ,  ), ( ,  ) adjacent        avoid race – – 100 – – 100 – – – – 100 – – – – – – – – – – – – – – 000 – – – – – –  

o Single transition time state assignment     – – – –   Y 1 = f(y 1, y 2, y 3, x 1, x 2 ) Y 2 = f(y 1, y 2, y 3, x 1, x 2 ) Y 3 = f(y 1, y 2, y 3, x 1, x 2 ) 13. State Identification and Fault-Detection Experiment a machine : reduced, completely specified a machine (block box) I Z A block box which cannot inspect the internal device and their interconnection.  The experiment consists of a set of inputs and their corresponding output sequences.  Identify the unknown initial state and the final state of the machine.  Equivalent to fault-detection problem to determine whether the machine is operating correctly.

o Homing sequence: to identify the final state. The input sequence which, when applied starting in any initial state, allows the final state to be uniquely determined by observing the output sequence produced. C/0 B/0 D/1 C/0 A/1 A/0 C/0 D/0 ABCDABCD 0 1 I S (A, B, C, D) (C) (A, D) 10 (A) (C) Input seq: 00 Output seq: 01  A Output seq: 10  C All machine has homing sequence o Synchronizing sequence: the input sequence which drives a machine to a known state, independent of the output sequence produced. A/1 B/0 B/0 C/0 C/0 D/0 D/1 D/1 ABCDABCD 0 1 I S (A, B, C, D) 0 1 (B, C, D) 0 1 (C, D) 0 1 (D) 111: synchronizing sequence

A/0 B/0 B/1 D/0 C/1 A/0 C/0 A/1 ABCDABCD 0 1 I S (A, B, C, D) 0 1 (A, B, C) (A, B, D) 0 1 (A, B, C) 0 1 (A, B, D) (A, B, C)(A, B, D) This machine does not have synchronizing sequence