1. Sequential Circuit Synthesis - II
Virendra Singh
Indian Institute of Science
Bangalore
IEP on Digital System Synthesis, IIT Kanpur

2. Incompletely Specified Machine
The specified behaviour of a machine with partially specified transitions can be described by another machine whose state transitions are completely specified
The transformation is accomplished by replacing all the dashes in the next state entries by T and adding a terminal state T whose output are unspecified PS
NS, z
X = 0
X = 1 A
B, 1
T, -- B
T, 0
C, 0 C
A, 1
B, 0 T PS
NS, z
X = 0
X = 1 A
B, 1
--, -- B
--, 0
C, 0 C
A, 1
B, 0
Dec 14,2007

3. Compatible States
State Si of M1 is said to cover, or contain, state Sj of M2 if and only if every input sequence applicable to Sj is also applicable to Si, and its application to both M1 and M2 when they are initially in Si and Sj, respectively, results in identical output sequences whenever the outputs of M2 are specified
Machine M1 is said to cover machine M2 if and only if, for every state Sj in M2, there is a corresponding state Si in M1 s.t. Si covers Sj
Dec 14,2007

4. Compatible States
Two states Si and Sj of machine M are compatible, if and only if, for every input sequence applicable to to both Si and Sj, the same output sequence will be produced whenever both outputs are specified and regardless of whether Si or Sj is the initial state
Si and Sj are compatible, if and only if, their outputs are not conflicting (i.e., identical when specified) and their Ii-successor, for every Ii for which both are specified, are the same or also compatible.
A set of states (Si, Sj, Sk, ….) is called compatible if all its members are compatible
Dec 14,2007

5. Compatible States
A compatible Ci is said to be larger than, or to cover, another compatible Cj, if and only if, every state in Cj is also contained in Ci
A compatible is maximal if it is not covered by any other compatible
Dec 14,2007

6. Compatible States PS NS, z X = 0 X=1 A C, 1 E, 1 C B, 0 A, 1 D D, 0 E
AE - α
β, 1
α, 0
BCD - β
β, 0
α, 1
Dec 14,2007

7. Compatible States PS NS, z X = 0 X=1 A A, 0 C, 0 B B, 0 B, -- C A, 1
A set of states is compatible if and only if every pair of the states in that set is compatible PS
NS, z
X = 0
X=1 A
A, 0
C, 0 B
B, 0
B, -- C
A, 1 PS
NS, z
X = 0
X=1 A
A, 0
C, 0 B’
B’, 0
B’’, --
B’’
B+, 0
B’, 1 C
A, 1
Dec 14,2007

8. Compatible States PS NS, z X= 0 X=1 (AB’) – α α, 0 β, 0 (B”C) – β α, 1
Dec 14,2007

9. Merger Graph PS NS, z I1 I2 I3 I4 A --- C, 1 E, 1 B, 1 B E, 0 C F, 0
Transforming into fully specified machine may not be optimal one
First generate the entire set of compatibles
Select an appropriate subset, which will form the basis of state reduction leading to minimum machine PS
NS, z I1 I2 I3 I4 A
---
C, 1
E, 1
B, 1 B
E, 0 C
F, 0
F, 1 D E
A, 0
D, 1 F
C, 0
B, 0
Dec 14,2007

10. Merger Graph
A set of states is compatible if and only if every pair of states in that set is compatible
It is sufficient to consider pair of states and use them to generate entire set
Compatible pair of states is referred as compatible pairs
Let the Ik-successors of Si and Sj be Sp and Sq, respectively; then (Sp Sq) said to be implied by (SiSj)
(SpSq) are referred as implied pair
Dec 14,2007

11. Merger Graph Merger graph is undirected graph
It consists of n-vertices, each of which corresponds to a state of M
For each pair of states (Si Sj) in M whose next state and output entries are not conflicting, an undirected arc is drawn between vertices Si and Sj
If for a pair of states (Si Sj) the corresponding outputs under all inputs are not conflicting, but successors are not the same, an interrupted arc is drawn between Si and Sj, and then implied pairs are entered in the space
Dec 14,2007

12. Merger Graph PS NS, z I1 I2 I3 I4 A --- C, 1 E, 1 B, 1 B E, 0 C F, 0D E
A, 0
D, 1 F
C, 0
B, 0
(CF) B F
(CF)
(AB)
(CD)
(EF)
(BE) C E D
Dec 14,2007

13. Merger Graph Merger graph is undirected graph Nine compatible pairs
(AB), (AC), (AD), (BC), (BD), (BE), (CD), (CF), (EF)
(AB), (AC), (BC) are compatible => (ABC) compatible
Find minimal set of compatible
{(ABCD), (BC), (BE), (DE)}
Dec 14,2007

14. Merger Graph
A set of compatible (for machine M) is said to be closed if, for every compatible contained in the set, all its implied also contained in the set.
A closed set of compatibles which contains all the sates of M is called closed covering
A set {(AD), (BE), (CD)} is a closed covering PS
NS, z I1 I2 I3 I4
(AB) - α
δ, 0
β, 1
δ, 1
α, 1
(CD) - β
---
(EF) - δ
β, 0
α, 0
Β, 0
Dec 14,2007

15. Compatible Graph
The compatible graph is a directed graph whose vertices corresponding to all compatible pairs, and arc leads from vertex (Si Sj) to vertex (Sp Sq) if and only if (Si Sj) implies (Sp Sq)
It is a tool which aids in the search for a minimal closed covering
Compatible pairs are obtained from merger graph
Dec 14,2007

16. Compatibility Graph PS NS, z I1 I2 I3 I4 A --- E, 1 B C, 0 A, 1 B, 0 C
D, 1
A, 0 D
B, -- E
C, --
(CF)
(BE)
(BC) B E
(AE)
(BC)
(BC)
(AB)
(AD) D
(DE) C
Merger Graph
Dec 14,2007

17. Compatibility Graph A AC (CF) (BE) (BC) B E AD (AE) BE (BC) (BC) (AB)
(DE) CD C DE
Merger Graph
Dec 14,2007

18. Minimization using Network Model
Behaviour of sequential circuit can be described by traces, i.e., sequence of inputs and outputs
Various approaches to optimize
Ignore registers and optimize the combinational logic
Retiming – move position of registers only
Dec 14,2007

19. Retiming
Minimize cycle time or the area of synchronous circuits by changing the position of the registers
Cycle time is bounded from below by the critical path delay in the combinational circuit
Retiming aims at placing the registers in the appropriate position, so that the critical paths they embrace are as short as possible
Moving registers may increase or decrease the number of regsisters
Dec 14,2007

20. Retiming + + +
Host δ δ δ δ
Dec 14,2007

21. Dec 14,2007

22. Dec 14,2007

23. Example P0 = (ABCDEFG) P1 = (ABCDFG) (E) P2 = (AF) (BCDG) (E)
Machine M2
P0 = (ABCDEFG)
P1 = (ABCDFG) (E)
P2 = (AF) (BCDG) (E)
P3 = (AF) (BD) (CG) (E)
P4 = (A) (F) (BD) (CG) (E)
P5 = (A) (F) (BD) (CG) (E) PS
NS, z
X = 0
X = 1 A
E, 0
C, 0 B
A, 0 C
B, 0
G, 0 D E
F, 1 F
D, 0 G
Dec 14,2007