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CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 11 February 23 W’05 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200.

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Presentation on theme: "CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 11 February 23 W’05 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200."— Presentation transcript:

1 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 11
February 23 W’05 Yutao He 4532B Boelter Hall

2 Outline Administrative Matters Chapter 7
Specification of Sequential Systems State Minimization

3 Administrative Matters
Project #2 Is posted on the web Due on March 2 (Wednesday) Teamwork is allowed and encouraged Find your partner as early as possible Homework #7 Midterm Will be handed back and discussed on Next Monday

4 Sequential Systems: Overview
Basic Concepts Synchronous sequential systems Clocks States Finite state machines Mealy and Moore machines Specification Time behavior (I/O sequence) State transition table State diagram Minimization Analog Digital Sync. Async. Comb. Seq. (Hardware) Systems

5 Definition of Sequential Systems

6 Sync. Vs. Async. Sequential Systems
Synchronous Asynchronous

7 Clock An independent periodic reference signal Provided by
An internal crystal An external 60 Hz alternating current Make sure you know When is the present (t) When is the next (t+1) back to the future When is the previous (t-1) forth to the past

8 Time-Behavior Specification
Behavior of a sequential system can be specified by a sequence of input(s)/output(s) pairs with respect to the clock signal Time t Input xi(t) Output zi(t)

9 Example 7.1: Serial Decimal Adder
Addition is performed one digit at a time, starting from the LSB Output is generated at each time instant As a result, a 8-digit serial decimal adder needs 8 clock cycles to finish the calculation s = x + y = t x(t) y(t) s(t) c(t)

10 State Introduced to help “memorize” the complete input/output sequences Usually number of states are finite Itself is also a time function Two types of states are defined: present state (PS): s(t) next state (NS): s(t+1)

11 State Description of Sequential Systems
A sequential system can be specified as a finite state machine (FSM) by specifying output function: z(t) = H(s(t), x(t)) state transition function: s(t+1) = G (s(t), x(t)) Output Function State transition Inputs x(t) Outputs z(t) Present State s(t) Next State s(t+1)

12 Example 7.3 - Serial Decimal Adder
Inputs: x(t), y(t)  {0,1, …, 9} Outputs: z(t)  {0, 1, …, 9} State: c(t)  {0, 1} Initial State: c(0) = 0 Functions: State transition function: c(t+1) = Output function z(t) = (x(t)+y(t)+c(t)) mod 10 1 if x(t)+y(t)+c(t)  10 0 otherwise

13 State Transition Table
An extended truth table for specifying output function and state transition function in a tabular form PS Inputs x(t) NS, Outputs z(t)

14 Example 7.4: Odd/Even Detector
Given a system whose input has two values a and b, and whose output also has two values, 0 and 1. The output at time t is 1 if the number of b’s in the input x(0,t) is even, and 0 otherwise. Inputs: x(t)  {a,b} Outputs: z(t)  {0, 1} State: s(t)  {Even, Odd} Initial State: s(0) = Even PS Inputs x(t) a b NS, Outputs z(t) Even Even, Odd, 0 Odd Odd, Even, 1 t x(t) a b b a b a b a z(t)

15 State Diagram A graphical specification of a sequential system

16 Example: State Diagram
PS Inputs x(t) a b NS, Outputs z(t) Even Even, Odd, 0 Odd Odd, Even, 1 b/0 b/1 a/1 a/0 Odd Even

17 Mealy and Moore Machines
Mealy Machine: Its output depends upon both input and state Moore Machine: Its output depends only upon present state inputs outputs state feedback reg combinational logic for next state logic for outputs state feedback inputs outputs reg combinational logic for next state logic for outputs Mealy Machine Moore Machine

18 Example 7.5 - A Moore Machine

19 How to Select State Names
Use integers as state names Example: A modulo-64 counter Input: x(t)  {0,1} Output: z(t)  {0,1,…,63} State: s(t)  {0,1,…,63} Initial State: s(0) = 0 Function: Transition function: s(t+1) = [s(t)+x(t)] mod 64 Output function: z(t) = s(t)

20 How to Select State Names (Cont’d)
Use state-vector approach: state is represented by a vector s = (sn-1, …, s 0) Example: A sequential system that counts the occurrence of 55 different events. When the count of event I is a multiple of 100, the output is z(t) = i, otherwise, z(t) = 0 Input: x(t)  {1, 2, …, 55} Output: z(t)  {0, 1, 2, …, 55} State: s(t) = (s55,…,s1), si  {0,1,…,99} State: s(0) = (0,0,…,0) Functions: Transition function: si(t+1) = Output function: z(t) = [si(t)+1] mod if x(t) = i si(t) otherwise i if x(t) = i and si(t) = 99 0 otherwise

21 Case Study 1: Finite Memory Systems
A sequential system has finite memory of length m is z(t) depends only on the last m input values: z(t) = F(x(t-m+1), t)) Example 7.12: z(t) = Finite memory of length four All finite-memory machines are FSMs Not all FSMs are finite-memory p if x(t-3,t) = aaba q otherwise 1 if number of 1’s in x(0, t) is even 0 otherwise

22 Case Study 2: Pattern Detector
Detect sub-patterns in the input sequence Two types: overlapped and non-overlapped Example: Input: x(t)  {0,1} Output: z(t)  {0,1} Function: z(t) = 1 if x(t-3,t) = 1101 0 otherwise

23 Case Study 3: Controller
A FSM that produces control signals as the states are traversed. Control signals determine actions performed by other parts of the system. Two types Autonomous State transitions follow a fixed sequence of states, independent of any inputs except the clock. Non-autonomous The transition is decided by external inputs

24 Vending Machine Controller

25 Vending Machine Controller (Cont’d)

26 State Minimization Motivation: Basic concept: Basic Methods:
High-level design may generate many redundant states Fewer states may mean fewer state variables To reduce the complexity and cost Basic concept: Two states are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same (1) Output must be the same in both states (2) Must transition to equivalent states for all input combinations Basic Methods: Table matching Implication Chart

27 Table Matching Procedure - Overview
Starting with the state table Step 1: Row matching with respect to outputs Step 2: Rename the newly partitioned classes Step 3: List their next state transitions by using new names Step 4: Check if partitions are same by column matching within classes If no, go back to Step 1 If yes, The states are minimal Write the state table for the minimal states

28 State Minimization - Example 7.14

29 Example 7.14 (Cont’d) Row Matching: Column Matching:
P1 = (A, C, E) (B, D, F) Column Matching:

30 Example 7.14 (Cont’d) Row Matching: Column Matching: Row Matching:
P2 = (A, C, E) (B, D) (F) Column Matching: P3 (A, C) (E) (B, D) (F) a b c Row Matching: P3 = (A, C) (E) (B, D) (F) Column Matching:

31 Example 7.14 (Cont’d) Column Matching: Stop: The states are minimal
P4 = (A, C) (E) (B, D) (F) = P3 Stop: The states are minimal

32 Summary Specification of sequential systems
time-behavior state-transition table equation state diagram Several common types of sequential systems pattern detectors controller State Minimization

33 Next Lecture Chapter 8: Sections


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