RBSP EFW DFB Peer Review 2009 Sept 10 1 EFW DFB Board-Level Testing Peer Review David Malaspina 2009 Sept 10

RBSP EFW DFB Peer Review 2009 Sept 10 2 Analog Circuitry Verification Plan 2 Signal into DFB Analog Electronics From ADC to FPGA Record (raw) waveforms at 16KS/sec FPGA pass data through Analyze waveforms in IDL (Function Generator) (GSE / Labview) (No FPGA processing on 16 KS/s data) (Compare results with specs.)

RBSP EFW DFB Peer Review 2009 Sept 10 3 GainsOffsets Power drawCommon mode rejection NoiseCrosstalk Square wave responseAnalog filter characterization Clipping responseTemperature variation* response* * Planned test Analog Circuitry Verification Plan

RBSP EFW DFB Peer Review 2009 Sept 10 4 FPGA Verification Plan 4 Signal into DFB Analog Electronics From ADC to FPGA Record (raw) waveforms at 16kHz IDL formatting of data for ALU module simulation FPGA processing Compare FPGA, Simulation & IDL results IDL routines performing same tasks as FPGA FPGA Simulation FPGA output

RBSP EFW DFB Peer Review 2009 Sept 10 5 Digital filtersDigital filter banks / triggers Field rotation* Defaults load on power up* Spectra* Cross-spectra* Solitary wave counter* Overclocking* *Planned test FPGA Verification Plan

RBSP EFW DFB Peer Review 2009 Sept 10 6 Configuration Verification Plan Verify commanding functionality –Start by testing nominal / default configuration –Can not test every possible configuration (thousands for filter banks alone) –Instead, test each configuration option fully, one at a time (31 possible for filter banks) 6

RBSP EFW DFB Peer Review 2009 Sept E12 DC Configuration Verification Plan E34 DC E56 DC SCM3 … E12 DC E34 DC E56 DC SCM3 … 1/16 S/s 1/8 S/s 1/4 S/s … 64 S/s On Off On Off 7 bins 13 bins S1(10) S2(10) Speed(11) En (2) En(2) Bands(2)

RBSP EFW DFB Peer Review 2009 Sept E12 DC Configuration Verification Plan E34 DC E56 DC SCM3 … E12 DC E34 DC E56 DC SCM3 … 1/16 S/s 1/8 S/s 1/4 S/s … 64 S/s On Off On Off 7 bins 13 bins S1(10) S2(10) Speed(11) En (2) En(2) Bands(2)

RBSP EFW DFB Peer Review 2009 Sept E12 DC Configuration Verification Plan E34 DCE56 DCSCM3 … E12 DC E34 DC E56 DC SCM3 … 1/16 S/s 1/8 S/s 1/4 S/s … 64 S/s On Off On Off 7 bins 13 bins S1(10) S2(10) Speed(11) En (2) En(2) Bands(2)

RBSP EFW DFB Peer Review 2009 Sept Example Analog Test Results Input: 4.9 Vpp Sine wave, variable Freq. *Without flight-like matching of caps and resistors

RBSP EFW DFB Peer Review 2009 Sept Example Analog Test Results Input: 1 kHz 4.9 Vpp or 9.5 Vpp Sine wave on input channel, all others terminated by 50 ohm resistor. * Results for outdated analog and digital ground plane connection configuration

RBSP EFW DFB Peer Review 2009 Sept Example Analog Test Results 1% overshoot Input: 1 kHz 1 V square wave

RBSP EFW DFB Peer Review 2009 Sept Example FPGA Test Results Input: 2.4 Vpp Sine wave, variable Freq. *Need to repeat at full range, all channels

RBSP EFW DFB Peer Review 2009 Sept END