1. FGM CDR
FGM Electronics (FGE)
Ronald Kroth
MAGSON GmbH
Berlin Germany

2. Fluxgate Electronic Electronics Design FGE Bread Board FGE ETU FGE FM
Excitation
Data Acquisition
Feedback
Housekeeping
Control
Power Dissipation
FGE Bread Board
Purpose of the Bread Board
Differences to the ETU’s and FM’s
Status of the Bread Board
FGE ETU
FGE ETU on the 6U Board
FGE ETU Layout
Status of the FGE ETU
Changes in the Layout since PDR
FGE FM
Status of the FM
Findings
Influence of Clock Jitter

3. Excitation to the sensor’s ringcore
Excitation signal, square wave, ca.10kHz
A square wave signal drives the excitation resonant circuit.

4. Data Acquisition
The pickup signal form the sensor is amplified by an instrumentation amplifier
and sampled by a 14-bit Analog-Digital Converter.

5. Feedback
The feedback voltage is generated by to cascaded 12-bit Digital to Analog Converters, acting as a “18-bit DAC”. The voltage is converted into the feedback current by a voltage driven precision current source.

6. Housekeeping
Two analog housekeeping signals are supplied, representing the sensor- and electronics temperature. A Pt100 in a resistor bridge is used to generate the signals.

7. Control
The FGE electronics is controlled by a FPGA which overtakes the following tasks:
Generating the Excitation Signal
Reading the ADC Data
Generating the Feedback Values
Calculating the Output Data
Acting as Command Receiver and Data Transmitter

8. Power Dissipation
The estimated power dissipation is made up by the following contributions :
Excitation 180mW
Preamplifier 180mW
Analog/Digital Converter 150mW
Feedback 200mW
FPGA mW (85mW)
Total mW (795mW)

9. The purpose of the FGE Bread Board is
to test and verify the general electronics design
to test and verify the FPGA design
to test the sensors
Differences to the FGE ETU’s and FM’s
There are some differences between the Bread Board Design and the ETU respectively FM design:
the Bread Board uses a re-programmable ProAsic FPGA
the FPGA core voltages are generated on board by line regulators
there are additional buffers in the digital lines due to the 3.3V IO’s of the ProAsic
the Bread Board has an additional parallel processor interface

10. Status
The Bread Board is used to test the general electronics design and the FPGA design along with a GSE supplied by the IWF Graz
Layout of the Bread Board

11. FGM ETU U6 Board with PCB
The FGE will co-reside with the PCB on a single 6U board.
The FGE will be placed on the opposite half of J1 connector site.
Space
for the
PCB Layout
6U Board with the FGE Layout

12. Layout to the back plane to the front panel to the PCB
Feedback DAC’s and Current Sources
Relays
Voltage Reference
to the
back
plane
to the
front
panel
Control FPGA
ADC’s
Preamplifiers
Serial Interface
Excitation
Power Interface
to the PCB

13. Status of the FGE ETU
The FGE ETU is delivered and ready for testing

14. Changes since PDR There have been the following changes in the FGE
design and layout since the PDR:
all DAC’s are now placed on the top side due to the limited space between the boards
Megatron precision resistors have been replaced by MIL-qualified Vishay types
WIMA high value capacitors in the excitation circuitry have been replaced by MIL-qualified Kemet types

15. Changes since PDR grounding concept has been improved:
separate ground nets for all functional parts,
connected at a star point close to the Power interface
ADC analog interface simplified and improved
based on experience of Venus Express
ADC serial interface mode was changed
the ADC will now be clocked by the system clock instead of using the ADC‘s internal clock
- no need to synchronise ADC clock to the system clock
- reduces potential interfering frequencies on the board

16. Status of the FM The FGE FM layout will base on the ETU layout
Modifications may be caused by:
the testing results of the ETU
the interconnection of the FGE and PCB layout

17. Influence of Clock Jitter (F1)
A jitter of the system clock will result in
a jitter in the excitation signal
an asymmetry of the excitation
increased noise in the magnetic field data
Test with a jittering excitation signal:
the excitation signal jittered with 0.1%
noise increased by the factor 3

18. Influence of Clock Jitter (F1)
A jitter of the system clock will result in
a jitter in the excitation signal
an asymmetry of the excitation
increased noise in the magnetic field data
Jittering excitation signal (tested with the VEX electronics):
the excitation signal jittered with one sys clock period (0.13%)
- noise increased by the factor 3
- influence of sys clock jitter will be neglectable