1 Microprocessors CSE - 341

2 Protected Mode Memory Addressing Remember using real mode addressing we were previously able to address 1M Byte of memory. Using Protected Mode memory addressing locations above the 1M byte boundary can be addressed. The Protected Memory scheme still uses base address and index address to calculate actual memory locations but, this is done in a different way from what we had done previously.

3 The offset address is still used as previously, to find the memory location within the segment that we are interested in. The use of the base or the segment address has changed a bit. The segment register now contains a selector rather than the “actual” base address of the segment. An additional table called a descriptor table uses the selector as an index to provide additional information known as descriptor. The descriptor describes: location Length Access rights For the segment of interest.

4 The actual instructions used for both real mode memory access and protected mode memory access may remain the same. This is because again the value stored in the segment register and the index register are used to obtain the actual memory location. The difference in the two modes comes the from way the microprocessor interprets the data present in the two registers to perform the memory location calculations. Another difference is that the offset address can be a 32-bit number instead of a 16 bit number in the protected mode. A 32 bit offset address allows the microprocessor to access data within a segment that can be 4G bytes in length.

5 There are two descriptor tables. Global Descriptor table and local descriptor table. Each table contains 8192 descriptors. Global descriptors contain segment definitions that apply to all programs. – System Descriptor. Local Descriptors provide information that are unique to an application. – Application Descriptor. Because each table contains 8192 descriptors, there are a total of descriptors available to any application. This also now means that up to memory segments could be described to be used by each application.

6 Why do you think we have only 8192 descriptors and not 64K ? Descriptor Access RightsBase (B23-B16) Base (B15 – B0) Limit (L15 –L0) through P4 Descriptor Base (B31-B24) GD0AVAV Limit (L19-L16) Access RightsBase (B23-B16) Base (B15 – B0) Limit (L15 –L0)

7 Base Address – Starting location of the memory segment has 24 bits allocated to storing the base address. 16 MB Memory locations and above use 32 bits for storing the base address. 4GB of memory locations is Upward computable because its MSB above the 24 bits are 0000

8 Segment Limit – The last possible offset address of the segment. So if the segment begins at memory location F00000H and ends at location F000FFH. What should be the value of the limit register ? Remember the limit registers size on is 16 bits and and above is 20 bit. Additional bits available to and above G – Granularity bit – If G =0 – The limit specifies segment limit of 00000H to FFFFFH. If G =1 – The limit specifies segment limit of 00000XXXH to FFFFFXXXH.

9 This increases the limit and allows the segment length of 4K to 4G bytes in steps of 4K Bytes has 16 bits to define offset because of its internal architecture and above have 32 bits and have a 32 bit internal architecture. Thus operating systems also work in either 16 bit mode or 32 bit mode. DOS works uses 16 bit environment and windows uses 32 bits.

10 Example: Segment start and end if the base address is H, the limit is 001FFH and G bit =0. Base = Start = H G =0 End = Base + Limit = H + 001FFH = FFH

11 Example: Segment start and end if the base address is H, the limit is 001FFH and G bit =1. Base = Start = H G =1 End = Base + Limit = H + 001FFXXXH = 101FFFFFH

12 AV – Available AV =1 – Available AV =0 – Not Available. D = Data access D = 1 – The instructions are in 32bits and the registers are 32 bits. D = 0 – The instructions are 16 bit instructions compatible with

13 Access Rights bytes- Control access to protected mode memory segment. This byte describes how the segment functions in the system PDPLSEED/CR/WA A = 0 – Segment Not Accessed A =1 – Segment has been accessed E = 0 Descriptor describes data segment ED = 0 Segment expands upwards ED =1 Segment expands downward W = 0 Data may not be written W =1 Data may be written

14 E = 1 Descriptor describes code segment C =0 Ignore descriptor privilege level C =1 Abide by privilege level R=0 Code segment may not be read R =1 Code segment may be read S =0 System descriptor S =1 Code or data segment descriptor DLP = sets the descriptor privilege level ( 00 – 11) P = 0 Descriptor is undefined P =1 Segment contains a valid base and limit

15 SelectorTIRPL Selector – Selects one of the 8192 descriptors. TI – Chooses either the global descriptor table or the local table. T1 = 0 – Global descriptor table T1 =1 – Local descriptor table RPL – Requested privilege level. 00 – highest 11 - lowest

16 DS 0008 Descriptor 0 Descriptor 1 Descriptor 2 Descriptor 3 Descriptor 4 Descriptor 5 Descriptor 6 Descriptor 7 Descriptor 8 Descriptor 9 Descriptor 10 Descriptor 11

17 DS 0008 FF Data Segment FF

18 Note : Descriptor 0 is called null descriptor and may not be used for accessing memory. Just like the stack the addresses of these descriptor tables have to be specified for the microprocessor. For this purpose and above microprocessors contain program invisible registers. These registers are not directly addressed by software and hence are given this name. These registers are used to control the microprocessor when operating in protected mode.

19 CS DS ES SS FS GS Segment Registers Descriptor Cache Base AddressLimitAccess TR LDTR Base AddressLimitAccessDescriptor Table addresses GDTRBase AddressLimit IDTR

20 The program invisible parts are known as CACHE. DO NOT confuse with cache memory L1 and L2. Once a code segment is loaded with the base address of the segment the descriptor cache is loaded with the details. The details are not changed until the value in the code segment register is updated. This increases efficiency as the values in the cache descriptor can be reused. Hence, the term cache is used for the invisible registers.

21 GDTR – Global descriptor table register. The base address of the descriptor table and its limit. The limit of each descriptor table is 16 bits because the maximum length of the table is 64K bytes. When protected mode operation in desired the values are loaded in the GDTR. IDTR – Interrupt descriptor table register. The base address of the descriptor table and its limit. The limit of each descriptor table is 16 bits because the maximum length of the table is 64K bytes. When protected mode operation in desired the values of the IDTR must also be initialized. We will deal with this later.

22 LDTR – Local descriptor table register. The LDTR does not hold the direct address of the local descriptor table. Instead it hold a selector just as the segment registers. The selector selects a descriptor in the global address table which points to the location of the local descriptor table. The base address of the LDT is then loaded in the LDTR. TR – Task Register Holds a selector which access a descriptor that defines a task. Task can be procedure or application program. The descriptor for the task is stored in the GDT so access can be controlled. Task register allows fast context switching helping in tasks that are often used or in multi-programming.

23 Memory Paging The memory paging mechanism located within the and above allows any physical memory location to be assigned to any linear address. The linear address is defined as the address generated by a program. Within the memory paging unit the linear address is invisibly translated into any physical address.

24 Quiz In question 2 the word actually should be actual