1. Chapter 8.3: Memory Management

2. Chapter 8: Memory Management
Background
Swapping
Contiguous Allocation
Chapter 8.2
Paging
Chapter 8.3
Segmentation
Segmentation with Paging

3. Segmentation
As it turns out, programmers do not view their address space as contiguous storage – rather they think of it as hunks of functionality and data.
Segmentation is a memory-management scheme that supports a user view of memory
A program is a collection of segments. A segment is a logical unit such as:
main program,
procedure,
function,
method,
object,
local variables, global variables,
common block,
stack,
symbol table, arrays

4. User’s View of a Program
In this view, a logical address space is a collection
of segments – each of which has a:
name and a
length.
An address is uniquely specified by the
segment name plus an offset ‘into’ the segment.
A user, therefore, must specify an address with
these two quantities.
Remember, paging has the user specify a single
address which is then mapped by hardware into
a page number (page frame) and an offset
– all transparent to the programmer.
Segmentation is NOT transparent to the user,
as we shall see.

5. Logical View of Segmentation1 4 2 3
Insofar as implementation is concerned,
segments are referred to by a segment
number rather than by name, as stated.
So a logical address has the format:
<segment number, offset>
Compilers that generate code to be
run in a segmented memory system
generate code that is reflective of the
program: Consider a C program:
The compiler will generate:
e.g. Code, global variables,
a heap from which memory is allocated,
a stack used by each thread
the standard C library, and more.
The loader makes sure that all these segments
are assigned segment numbers.
Displacements within each segment is moot. 1 2 3 4
user space
physical memory space

6. Segmentation Architecture
So, how do we implement a logical address consisting of:
<segment-number, offset>?
We map a two-dimensional item into one-dimensional space, primary memory.
This is accommodated by using a data structure called a segment table.
Each segment table entry has a segment base and a segment limit.
Clearly the segment base is the starting address of the segment while the limit is the length of the segment in real memory.
A logical address then, consists of a
segment number, s, and
an offset into that segment, d. So we can say, <s, d>
As it turns out, the segment number, s, is used as an index into a segment table, and the displacement, d, must be less than the segment limit.
For a legal reference, the displacement is added to the segment base to produce the address in physical memory of the desired byte.
The segment table is, really in truth, a table or array of base-limit register pairs.
Consider the following slide that says it all:

7. Address Translation Architecture
See logical address,
<s,d>. (Note that these are
produced by the compiler)
s is an index into the
segment table.
Assuming there is a hit,
the limit is compared to
the d(isplacement) from
the logical address.
If d < limit, then d is added
to the base to form the
physical address of the
desired memory byte.
The segment base is the
location of the indexed segment
in physical memory.

8. Example of Segmentation
Consider this example:
We have five segments as shown.
Each has a segment number and a length.
(Notice length attributes of each
segment in the segment table
indexed by the segment number…
Segment table has a separate entry
for each segment.
So, if we reference byte 53 of segment 2,
we first notice that segment 2 does exist.
Further, the limit of segment 2 is 400
and d(isplacement) is 53, which is < 200.
Thus the read memory address of the
desired byte is =4353.
Pretty straightforward.

9. More
A couple of architectural items not mentioned in your text include a:
Segment-table base register (STBR) which points to the segment table’s location in memory, and a
Segment-table length register (STLR) which indicates number of segments used by a program;
segment number s is legal if s < STLR

10. Segmentation Architecture (Cont.)
Just as in paging, we may add a wee bit of hardware to handle:
Protection: bits associated with segments;
validation bit = 0  illegal segment
read/write/execute privileges
Code sharing occurs at segment level
The notion of code sharing is very important to segments…
Does this require reentrant code?
Consider the following slide:

11. Sharing of Segments Segment table for each
process:
What does this tell you about sharing?
Does it suggest anything regarding
the need for reentrant code?
What say you? (see questions at
end of this set of slides).
Sharing? Discuss…

12. Segmentation with Paging – Intel 386
Both paging and segmentation have advantages and disadvantages.
Some architectures have both.
The Intel family of microprocessors has both pure segmentation and segmentation with paging as we shall see.
On Pentium machines, the CPU generates logical addresses which are provided to a segmentation unit.
This unit produces a linear address for each logical address.
This address is then presented to a paging unit which generates the physical address in memory.
So, the segmentation and paging units form the equivalent of the memory management unit (MMU).
As shown in the following diagram, the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme
Let’s look at this in a little more detail.

13. Pentium Segmentation
In the Pentium architecture, segment size can be as large as 4MB, while the maximum number of segments is 16K. Thus a ‘program’ can be huge!
The logical address space is divided into two partitions.
First partition consists of up to 8KB segments (8K = 8192); these are private to a process. (8K  13 bits are used for this…)
Second partition also consists of up to 8KB segments, and these are shared by all processes.
Local descriptor table (LDT) contains information about the first partition the private segments
Global descriptor table (GDT) contains information about the second partition, the shared segments.
Each entry in each of these segment tables consists of an eight-byte (64 bits) segment descriptor that contains detailed information about the segment including a base location and a limit for the segment it is describing.

14. Pentium Segmentation
The local address is a pair – a selector (16 bits) and an offset (32 bits) – where:
The selector is 16-bits and has the format: <s, g, p> where
‘s’ designates the segment number (13 bits), (last slide  8K segments!)
‘g’ designates whether the segment is in the Global Descriptor Table or the Local Descriptor Table, (1 bit) and
‘p’ are two protection bits.
The 32 bits of offset refers to displacement within the specified segment.
How does the Pentium uses this linear address to develop a 32-bit physical address.
Additional very detailed information:
The Pentium architecture has six segment registers, which allows up to six segments to be addressed at any one time by a process
This architecture also has six 8-byte micro-program registers to hold the corresponding descriptors from the LDT or the CDT.
This cache lets the Pentium avoid having to read the descriptor from memory for each memory reference.
The segment register points to the appropriate base in either the LDT or the GDT. Thus the base plus the limit data are used to generate a linear address.

15. 16 bits in the Global or Local Descriptor Table
16 bits <s, g, p> bits of offset
address
logical
selector offset
descriptor table (local or global)
Segment descriptor
s is segment number
Because there are
13 bits for segment
number, there can
be a huge number
of segments! (8K) +
32 bit linear address
But we are not done….. Onto paging in the Pentium………….

16. Pentium Paging
In the Pentium architecture, we know that one may have either 4K or 4MB pages.
And, for paging, the Pentium uses a two-level paging scheme that we are used to.
page number page offset
p p d
10 bits bits bits
The figure on the next page shows the details of Pentium paging in more detail.
The 10 high order bits reference an entry in the outermost page table called the page directory
The CR3 register in the Processor points to the current process’ page directory
The page directory entry points to an inner page table indexed by the innermost 10 bits from the linear address.
Lastly, the low-order bits 0-11 are added to account for the offset in the 4K page pointed to in the page table.
There’s also a single bit, in the page directory used to indicate whether the page size is 4K or 4MB.
If set, the mapping bypasses the inner page table and uses the 22 low-order bits from the linear mapping as the offset into the 4MB page size.
Interestingly from an efficiency perspective is that the page tables can be swapped to disk. If this is the case, the OS uses the other 31 bits to specify disk location of the page table.

17. Intel 30386 Address Translation
16 bits
32 bits
13 bits used
for selection
10 bits bits bits
Or 22 bits if pages are 4MB

18. Homework
Discuss paging and segmentation on a Pentium machine and compare this with the approach used by Linux for memory management.
What do you fee are the advantages / disadvantages of the Pentium architectural approach to memory management given other implementations of paging and segmentation in this chapter?

19. End of Chapter 8.3