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Memory Management Unit

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1 Memory Management Unit
Mrs. Shilpa S. Paygude

2 Architecture of 80386DX

3 80386DX Features Flexible 32-Bit Microprocessor
8, 16, 32-Bit Data Types 8 General Purpose 32-Bit Registers Very Large Address Space 4 Gigabyte Physical 64 Terabyte Virtual 4 Gigabyte Maximum Segment Size

4 Contd. Integrated Memory Management Unit Virtual Memory Support
Optional On-Chip Paging 4 Levels of Protection Virtual 8086 Mode Allows Running of Software in a Protected and Paged System Optimized for System Performance Pipelined Instruction Execution On-Chip Address Translation Caches 20, 25 and 33 MHz Clock

5 Previous members in x86 family
No Memory Management Unit Application program size limited to available memory (RAM) Single tasking environment Segment size maximum 64KB

6 Requirements of Efficient working Environment
Multitasking Protection –Restricted Access to Data , Code & Stack Secure Access to I/O devices With minimum available memory, execution of application of any size

7 Modes of Operation Real Address Mode Protected Mode Virtual 86 Mode

8 Protected Mode Features
Multitasking Protection Virtual Memory- Demand Paging

9 Significant Facts Microprocessor can execute one instruction at a time
Microprocessor works very fast ( in microseconds ) compared to human response time

10 Important Bits

11 Components of MMU Segmentation Unit : Deals with segments of a program . Paging Unit : Divides programs in fixed size (4KB) blocks.

12 Segmentation Unit Defines various types of segments with different attributes and provides segment level protection. Cannot be Disabled. It converts Logical Address to Linear Address.

13 Paging Unit Divides a program in fixed sized pages(4KB).
Swaps pages between RAM & secondary device as required. Provides page level protection. It converts Linear address to Physical address. Optional -can be enabled or disabled.

14 Address Translation Virtual / logical address to Linear Address
CS : IP  Base address + IP  Linear address Linear Address to Physical Address Linear Address  Base address from page table + offset

15 Segmentation Segmentation is one method of memory management.
Segmentation provides the basis for protection. Segments are used to encapsulate regions of memory which have common attributes. Segment selectors can be considered the logical “name” of a program module or data structure

16 What Are Segments? Segments are variable sized blocks of linear addresses which have certain attributes associated with them There are two main types of ( non system) segments: code and data Segments are of variable size - as small as 1 byte or as large as 4 gigabytes Base address (32bit) + Offset (32bit)  Linear Address Base address defined in the descriptor by system

17 A segment is described by a structure – Segment Descriptor
Each segment (Code/data/stack) has a unique descriptor in memory All descriptors are maintained in a table – Descriptor Table

18 Segment Registers

19 System Tables GDT (Global Descriptor Table),
IDT (Interrupt Descriptor Table), LDT (Local Descriptor Table), TSS (Task State Segment).

20 System Segment Registers

21 Global Descriptor Table (GDT), & GDTR
Segment base address (32 bit) GDT Segment Descriptor n Segment Descriptor 1 Segment Descriptor 0 NULL Descriptor Offset (32bit) Segment register + Selector GDTR Base Address Limit - 1 Linear address (32bit)

22 Details of Registers

23 Working Environment

24 How Segment Descriptor is accessed?

25 Global Descriptor Table
The Global Descriptor Table (GDT) contains descriptors which are possibly available to all of the tasks in a system. The GDT can contain any type of segment descriptor except for descriptors which are used for servicing interrupts (i.e. interrupt and trap descriptors). Every Intel386 DX system contains a GDT

26 Contd. Generally the GDT contains code and data
segments used by the operating systems and task state segments, and descriptors for the LDTs in a system. GDT contains descriptors for segments which are common to all tasks

27 Local Descriptor Table
LDTs contain descriptors which are associated with a given task. Generally, operating systems are designed so that each task has a separate LDT. The LDT may contain only code, data, stack, task gate, and call gate descriptors. There can be 0 or many LDTs.

28 LDTR The visible portion of the LDT register contains only a 16-bit selector. This selector refers to a Local Descriptor Table descriptor in the GDT. LDTs provide a mechanism for isolating a given task's code and data segments from the rest of the operating system

29 Descriptor Table Registers

30 Non System Segment Descriptor

31 System Segment Descriptor

32 Segment Level Protection

33 Privilege Level Privilege Level-One of the four hierarchical
privilege levels. Level 0 is the most privileged level and level 3 is the least privileged. More privileged levels are numerically smaller than less privileged levels.

34 Privileged Instructions
System tables are manipulated by the operating system. Therefore, the load descriptor table instructions are privileged instructions. The instructions that can be executed at CPL=0 are privileged instructions.

35 Memory Map

36 Paging Paging is another type of memory management useful for virtual memory multitasking operating systems Freed space of an outgoing task always same as that needed for an incoming task A page most likely corresponds to only a portion of a module or data structure

37 Components of the paging mechanism
The page directory The page tables The page itself (page frame)

38 Advantages A uniform size of 4KB for all of the elements simplifies memory allocation and reallocation schemes, since there is no problem with memory fragmentation. Protection can further be increased at page level.

39 Linear Address to Physical Address
Index to Directory Index to Table Offset in Page 4KB page Directory Entry Page Table Entry Base address Page PDBR CR3 Page Table Directory Page Table

40 Paging Mechanism

CR3 is the Page Directory Physical Base Address Register. It contains the physical starting address of the Page Directory. Page Directory is always page aligned. CR2 is the Page Fault Linear Address register. It holds the 32-bit linear address which caused the last page fault detected

42 PAGE DIRECTORY The Page Directory is 4K bytes long and allows up to 1024 Page Directory Entries. Each Page Directory Entry contains the address of the next level of tables, the Page Tables and information about the page table. Page Directory Entry points to Page Table

43 Page Directory Entry

44 PAGE TABLES Each Page Table is 4K bytes and holds up to Page Table Entries. Page Table Entries contain the starting address of the page frame and statistical information about the page Page tables can be shared between tasks and swapped to disks.

45 Page Table Entry

46 Page Level Protection The paging mechanism distinguishes between two levels of protection: User which corresponds to level 3 of the segmentation based protection, and supervisor which encompasses all of the other protection levels (0, 1, 2). Programs executing at Level 0, 1 or 2 bypass the page protection, although segmentation based protection is still enforced by the hardware.

47 Bits used for Protection
The U/S and R/W bits are used to provide User/Supervisor and Read/Write protection for individual pages or for all pages covered by a Page Table Directory Entry The U/S and R/W bits in the first level Page Directory Table apply to all pages described by the page table pointed to by that directory entry.

48 Page Level Protection The U/S and R/W bits in the second level Page Table Entry apply only to the page described by that entry. The U/S and R/W bits for a given page are obtained by taking the most restrictive of the U/S and R/W from the Page Directory Table Entries and the Page Table Entries

49 Translation Lookaside Buffer
Performance would degrade substantially if the processor was required to access two levels of tables for every memory reference. Intel386 DX keeps a cache of the most recently accessed pages, this cache is called the Translation Lookaside Buffer (TLB).

50 Translation Lookaside Buffer
The TLB is a four-way set associative 32- entry page table cache. It automatically keeps the most commonly used Page Table Entries in the processor. The 32-entry TLB coupled with a 4K page size, results in coverage of 128K bytes of memory addresses.

51 Translation Lookaside Buffer

52 TLB Hit The paging unit hardware receives a 32-bit linear address from the segmentation unit. The upper 20 linear address bits are compared with all 32 entries in the TLB to determine if there is a match. If there is a match (i.e. a TLB hit), then the 32-bit physical address is calculated and will be placed on the address bus.

53 TLB Miss Intel386 DX will read the appropriate Page Directory Entry. If P = 1 on the Page Directory Entry indicating that the page table is in memory, then the Intel386 DX will read the appropriate Page Table Entry

54 Paging Exceptions


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