1. 16.317: Microprocessor System Design I
4/14/2017
16.317: Microprocessor System Design I
Instructor: Dr. Michael Geiger
Spring 2012
Lecture 22: Virtual memory
Chapter 2

2. Microprocessors I: Lecture 22
Lecture outline
Announcements/reminders
Lab 2 due 3/28
HW 3 due 3/26
Lecture outline
Review
Local memory accesses
Interrupt descriptor table
Task switching
Virtual memory
Benefits
VM and segmentation
Paging
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Microprocessors I: Lecture 22

3. Microprocessors I: Lecture 22
Review
Local memory access
Selector indicates access is global (TI == 1)
LDTR points to LDT descriptor in GDT
Actual base, limit of LDT stored in LDTR cache
Index field in selector chooses descriptor from LDT
Descriptor addr = (LDT base) + (selector index * 8)
Descriptor provides starting address of segment
Interrupt descriptors
Provide starting address, length of interrupt service routines
Limited to 256 descriptors
Stored in IDT; IDTR holds base/limit of IDT
Task switching
Task register (TR): selector for current task state segment (TSS)
TSS stores all state (register values) for current task
Task switch: jump/call that changes TR; old TSS saved and new one loaded
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Microprocessors I: Lecture 22

4. Microprocessors I: Lecture 22
Problems with memory
DRAM may be too expensive to buy enough to cover whole address space
We need our programs to work even if they require more memory than we have
A program that works with 512 MB RAM should still work with 256 MB RAM
Most systems run multiple programs
Most processors don’t have hardware multitasking support (like the 386)
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Microprocessors I: Lecture 22

5. Microprocessors I: Lecture 22
Solutions
Leave the problem up to the programmer
Assume programmer knows exact memory configuration
Overlays
Compiler identifies mutually exclusive regions
Virtual memory
Use hardware and software to automatically translate references from virtual address (what the programmer sees) to physical address (index to DRAM or disk)
Most virtual addresses not present in physical memory!
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Microprocessors I: Lecture 22

6. Virtual Address and VA Space
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Virtual Address and VA Space
80386 virtual addresses: 48-bit
Used by Memory Management Unit (MMU)
Consists of
Selector (16bit): can be one of the segment selector register
Offset (32bit): can be EIP or other 32-bit registers
Segment can be as large as 4GB
Virtual address space can be 246 bytes (64 Terabytes)
2 bits used for privilege level in selector
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Microprocessors I: Lecture 22
Chapter 8

7. Microprocessors I: Lecture 22
Address translation
Virtual address  physical address
Need address translation mechanism
May take multiple steps
On 80386, two (main) levels
Virtual address (VA)  linear address (LA)
Uses selectors, descriptors discussed so far
Linear address  physical address (PA)
If using segmented memory model, PA == LA
If using paged memory model, translate LA to PA
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Microprocessors I: Lecture 22

8. Segmented Partition of Virtual Address Space
80386 virtual memory space is divided into global and local memory address space
32 Terabytes global address space
32 Terabytes local address space
Up to 8192 segments may exist in either global or local address space
Because maximum size of GDT is 64KBytes, each descriptor is 8bytes, 64KB/8B = 8192
Not all descriptors are normally in use
Task has both global and local memory space
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Microprocessors I: Lecture 22

9. Physical Memory Space and Virtual-to-Physical Address Translation
4GB physical memory vs 64TB virtual memory space
Just a small amount of the information in virtual memory can reside in physical memory
Segments not in use is stored on secondary storage device
Address translation: 48bit VA -> 32bit PA
Segment translation
Page translation
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Microprocessors I: Lecture 22

10. Microprocessors I: Lecture 22
Memory Swap
MMU determines whether or not a segment or page resides in physical memory
If not present, “swap”
memory management software initiates loading of the segment or page from external storage device to physical memory
A segment or page in physical memory will be swapped out and stored in external storage device
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Microprocessors I: Lecture 22

11. Segmentation Virtual to Physical Address Translation
48-bit virtual address (selector + offset) translated to 32-bit physical address
“Selector” used to find segment descriptor in LDT
64-bit segment descriptor cache register in contains:
access rights (12b), base address(32b), limit(20b)
Segment descriptor cache defines the location and size of code/data segment
Code/data segments in physical memory
Offset is the address of the data to be accessed in the segment
Segment base address + offset = 32b linear address
32b linear address is physical address, if paging is disabled
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Microprocessors I: Lecture 22

12. Microprocessors I: Lecture 22
Example
Segment selector = 0100H
offset = H
segment base address = H
Q:What is the virtual address? Physical address?
A: VA = 0100: H
linear address = base address + offset
= H H
= H
if paging disabled, PA = linear addr = H
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Microprocessors I: Lecture 22

13. Paged partition of Virtual Address Space
Physical memory is organized in 4KB pages
4GB/4KB = 1,048,496 pages
Simplifies the implementation of the memory management software
Fixed 4K pages make space allocation and deallocation easier than segmentation
Space in a page might not be fully utilized
Linear address is not direct physical address
Undergo a second translation - page translation
Format: 12-b offset, 10-b page, 10-b directory field
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Microprocessors I: Lecture 22

14. Managing virtual memory
Effectively treat main memory as a cache
Blocks are called pages
Misses are called page faults
Virtual address consists of virtual page number and page offset
Virtual page number
Page offset 31 11
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Microprocessors I: Lecture 22

15. Virtual address spaces
Page Table
OS manages the page table for each ASID
Physical
Memory Space
A valid page table entry codes physical memory “frame” address for the page
A virtual address space
is divided into blocks
of memory called pages
frame
frame
frame
A machine usually supports
pages of a few sizes
(MIPS R4000):
frame
A page table is indexed by a
virtual address
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Microprocessors I: Lecture 22

16. Microprocessors I: Lecture 22
Details of Page Table
Page Table
Physical
Memory Space
Virtual Address
Page Table
index
into
page
table
Base Reg V
Access
Rights PA
V page no.
offset 12
table located
in physical
memory
P page no.
Physical Address
frame
frame
frame
frame
virtual address
Page table maps virtual page numbers to physical frames (“PTE” = Page Table Entry)
Virtual memory => treat memory  cache for disk
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Microprocessors I: Lecture 22

17. Microprocessors I: Lecture 22
Paging on 80386
Two-level page table
First level: “page directory”
Starting address stored in CR3 (page directory base register (PDBR))
Indexed by upper 10 bits of linear address
Second level: “page table”
Starting address of each “page table” stored in page directory
Indexed by middle 10 bits of linear address
Provides starting address of physical page frame
Physical address = (page frame base) (offset)
Offset = lowest 12 bits of linear address
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Microprocessors I: Lecture 22

18. Virtual memory performance
Address translation accesses memory to get PTE  every memory access twice as long
Solution: store recently used translations
Translation lookaside buffer (TLB): a cache for page table entries
“Tag” is the virtual page #
TLB small  often fully associative
TLB entry also contains valid bit (for that translation); reference & dirty bits (for the page itself!)
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Microprocessors I: Lecture 22

19. Microprocessors I: Lecture 22
Next time
Virtual memory examples
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Microprocessors I: Lecture 22