Bus Architecture Memory unit AR PC DR E ALU AC INPR 16-bit Bus IR TR Access Select Memory unit 4096x16 111 S1 address S0 AR 001 PC 010 DR 16-bit Bus 011 E ALU AC 100 INPR IR 101 TR 110 OUTR clock CSC321

Instruction Format I opcode address I = 0 means direct memory address 15 14 12 11 I opcode address I = 0 means direct memory address I = 1 means indirect memory address CSC321

The Control Unit Control Unit Instruction Register (IR) 15 14 - 12 11 - 0 Other Inputs 3x8 Decoder 12 Control Unit D7 – D0 n I T15 – T0 4x16 Decoder Increment Sequence Counter Clear Master Clock CSC321

Decoding the Instruction We’ve seen how to fetch and decode instructions in RTL notation We now need to look at how to execute each instruction T0 T1 T2 = 1, register or I/O = 0, memory reference = 1, I/O = 0, register = 1, indirect = 0, direct T3 T3 T3 T3 CSC321

Input/Output Instructions Recall the I/O instructions posed a potential problem Their purpose is to set up loop structures waiting for an input/output device to become available This could cause large amounts of valuable time to be wasted CSC321

Interrupts To alleviate this problem we introduce interrupts into the system Two instructions enable and disable interrupts Sometimes we don’t want to be interrupted such as when we’re doing something important or we’re already servicing and interrupt ION (enable interrupts) D7IT3B7: IEN ← 1, SC ← 0 IOF (disable interrupts) D7IT3B6: IEN ← 0, SC ← 0 We also introduce another flip-flop, R, which tells the system when there is an interrupt to be handled CSC321

Interrupt Cycle Interrupts are subroutine calls with a couple of differences They come at arbitrary times during program execution The start address of the interrupt service routine (subroutine) is a predetermined, fixed location in memory CSC321

Interrupt Cycle Set up the interrupt service routine The interrupt service routine ends with a BUN to indirect address 0 = 0 = 1 = 0 = 1 = 1 = 0 I/O device is ready so signal an interrupt = 1 Once set-up, the system carries on as usual = 0 CSC321

Interrupt Cycle INTERRUPT SERVICE ROUTINE INTERRUPT SERVICE ROUTINE Interrupt cycle sets return address here and PC here PC is here when the interrupt occurred BUN 0x51 0x00 0x01 1 INTERRUPT SERVICE ROUTINE 0x10 0x11 0x11 BUN 0x51 0x00 0x01 1 INTERRUPT SERVICE ROUTINE 0x10 CSC321

Interrupt Cycle Implementation To implement the interrupt cycle we introduce the R flip-flop\ To utilize it we modify our fetch/decode RTL as follows CSC321

Modified Fetch/Decode It was this… We modify it to this… T0: AR ← PC T1: IR ← M[AR], PC ← PC + 1 T2: D0, … D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15) R’T0: AR ← PC R’T1: IR ← M[AR], PC ← PC + 1 R’T2: D0, … D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15) CSC321

Modified Fetch/Decode We must also add the interrupt cycle handler RTL… RT0: AR ← 0, TR ← PC RT1: M[AR] ← TR, PC ← 0 RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0 CSC321

Remainder of Chapter 5 The remainder of the chapter discusses how to convert the Control Unit RTL into logic gates This is really nothing more than defining AND/OR/NOT/XOR gates to handle the conditions on the RTL statements Thus, I’m not going to spend any time on it and won’t hold you accountable for it but… You should read it over once to get a feel for how all this stuff ties together CSC321

Homework Problems 5-9, 5-10, 5-11, 5-12 Due next lecture CSC321

Sequence Counter CPU Registers Memory Location SC PC IR AR DR I AC 135 5135 3160 DA00 2150 C135 FFFF 47 48 1355 1365 1375 1505 Initial Memory Contents 0C00 A0A0 01FF PC IR AR DR AC I 1 CSC321