Sequential Networks: Timing and Retiming Lecture 10: Sequential Networks: Timing and Retiming CSE 140: Components and Design Techniques for Digital Systems Fall 2014 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego

Timing Two timing constraints: Shortest and longest timing paths Flip-Flop timing window Combinational timing

Timing Clock specifies a precise time for the next state In general, we allocate one clock period for signal propagation between registers. Too late: Fail to reach for the setup of the next state. Too early: Race to disturb the holding of the next state. Analysis: Verify the timing of the system. Goal: A robust design.

So far …. Combinational CLK Logic-level analysis

This lecture … Combinational CLK When does our (seemingly logically correct) design go wrong? How can we design a circuit that works under real constraints?

Sequential Networks Combinational CLK1 CLK2 A B C D R1 R2 A typical sequential network has combinational circuit between registers (R1 to R2). The registers are synchronized by clocks (CLK1 to CLK2). Timing is set between clocks (CLK1 and CLK2). The beauty of the synchronized design is that we need only to take care of the timing of the regions separated by the registers.

iClicker C1 C2 CLK x(t) y(t) S(t) For a synchronized digital Moore machine, we need to take care of the timing of the following region(s). Between every pair of registers. Between i. input and register, and ii. register and output. Both A and B. Whole system from input to output including registers.

tcq + tcomb + tsetup ≤ T thold < tcq + tcomb Combinational CLK1  

max(tcq + tcomb + tsetup )≤ T Combinational CLK1 CLK2 A B C Setup time constraint tcq + tcomb + tsetup ≤ T Longest delay from CLK1 to CLK2 max(tcq + tcomb + tsetup )≤ T Hold time constraint thold < tcq + tcomb Shortest delay from CLK1 to CLK2 thold < min(tcq + tcomb)

Sequential Networks Timing: Setup Time and Hold Time Constraints D Q

Timing Constraints of flip flops D Q Q’ D t1 time What if the input transition happens late, close to the rising edge? Output will still be one at t1 Output will be zero at t1 Can’t say for sure

Input Constraints: Set up and hold time Q Q’ Setup time: tsetup Time before the clock edge that data must be stable (i.e. not change) Hold time: thold Time after the clock edge that data must be stable Aperture time: ta Time around clock edge that data must be stable (ta = tsetup + thold)

Set up and hold time violations Q Q’ Setup time violation This occurs if the input data signal does not remain unchanged for at least tsetup before the clock edge. Hold time violation This occurs if the input data signal does not remain unchanged for at least tsetup before the clock edge

Output Timing Constraints Propagation delay: tpcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing) Contamination delay: tccq = time after clock edge that Q might be unstable (i.e., start changing) D Q Q’

Output Timing Constraints D Q Q’ Contamination delay: tccq Time after clock edge that Q might be unstable (i.e., start changing) Propagation delay: tpcq Time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing)

PIQ: A hold time violation is likely to occur when The input signal (into the flip flop) fails to change to a desired value fast enough The output signal (out of the flip flop) takes too long to stabilize The input signal (into the flip flop) does not remain stable long enough after the clock edge The output signal (out of the flip flop) changes too quickly

PIQ: The timing of which of the following signals can cause a setup-time violation? T(t) T Q Q’ The input signal T(t) The output signal Q(t) The clock signal, CLK Some of the above None of the above CLK

PIQ: For a given flip-flop implementation which of its timing parameters can we modify when designing a sequential network (depicted below) Combinational CLK Set up and hold time Propagation and Contamination delays All of the above None of the above

Now let’s look at the timing characteristics of the combinational part Fact 1: Once a flip flop has been ‘built’ we are stuck with its timing characteristics: tsetup , thold, tccq, tpcq Combinational CLK Now let’s look at the timing characteristics of the combinational part

Combinational Logic: Output timing constraints circuit X1 Y1 X2 Y2 X3 Y3 X4 Y4 Why don’t we have input constraints?

Combinational Logic: Output timing constraints circuit X1 Y1 X2 Y2 X3 Y3 X4 Y4 Contamination delay: tcd Minimum time from when an input changes until any output starts to change

Combinational Logic: Output timing constraints circuit X1 Y1 X2 Y2 X3 Y3 X4 Y4 Contamination delay: tcd Minimum time from when an input changes until any output starts to change Propagation delay: tpd Maximum time from when an input changes until the output or outputs of a combinational circuit are guaranteed to reach their final value (i.e., stop changing)

Combinational Logic: Output timing constraints Y C D PI Q: Which path in the above circuit determines the contamination delay of the circuit (assuming the delay of all the gates is the same)? AND- OR – NOR AND-OR NOR OR-NOR

Combinational Logic: Output timing constraints Y C D PI Q: Which path in the above circuit determines the propagation delay of the circuit (assuming the delay of all the gates is the same)? AND- OR – NOR AND-OR NOR OR-NOR

An alternate view of the sequential circuit Combinational CLK R1 Combinational CLK R2 D1 Q1 D2

What should happen within a clock cycle for correct functionality? Combinational CLK R2 D1 Q1 D2

The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements (Dynamic Discipline)

PI Q: Suppose input to R1 changed before t1, what is the maximum delay (from t1) after which D2 reaches a stable value? Setup time of R1+ Propagation delay of CL + Propagation delay of R2 Hold time of R1+ Propagation delay of CL + setup time of R1 Propagation delay of R1+ Propagation delay of CL + Propagation delay of R2 Propagation delay of R1+ Propagation delay of CL Propagation delay of CL + Propagation delay of R2

Setup Time Constraint The setup time constraint depends on the maximum delay from register R1 through the combinational logic. The input to register R2 must be stable at least tsetup before the clock edge. Maximum delay, tmax = Setup Time Constraint:

Setup Time Constraint Tc ≥ tpcq + tpd + tsetup PI Q: As a designer, which of the following parameters would you modify to meet the set up time constraint? The clock period, Tc The prop. delay of R1, tpcq The prop. delay of CL, tpd The setup time of R2, tsetup All of the above

Setup Time Constraint Tc ≥ tpcq + tpd + tsetup tpd ≤ Tc – (tpcq + tsetup) PI Q: As a designer, which of the following parameters would you modify to meet the set up time constraint? The clock period, Tc The prop. delay of R1, tpcq The prop. delay of CL, tpd The setup time of R2, tsetup All of the above

PI Q: Suppose input to R1 changed before t1, what is the minimum delay (from t1) after which D2 starts to change? Setup time of R1+ propagation delay of CL + propagation of R2 Hold time of R1+ propagation time of CL +setup time of R1 Hold time of R1+ Contamination delay of CL + Propagation time of R2 Contamination delay of R1+ Contamination delay of CL Contamination delay of CL + Contamination delay of R2

Hold Time Constraint The hold time constraint depends on the minimum delay from register R1 through the combinational logic. The input to register R2 must be stable for at least thold after the clock edge. Minimum delay, tmin = Hold Time Constraint:

Hold Time Constraint thold < tccq + tcd tcd > thold - tccq

Timing Characteristics Timing Analysis Timing Characteristics tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps tpd = 35 ps tcd = 25 ps tpd = tcd = Setup time constraint: Tc ≥ fc = 1/Tc = Hold time constraint: tccq + tpd > thold ?

Timing Characteristics Timing Analysis Timing Characteristics tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps tpd = 35 ps tcd = 25 ps tpd = 3 x 35 ps = 105 ps tcd = 25 ps Setup time constraint: Tc ≥ (50 + 105 + 60) ps = 215 ps fc = 1/Tc = 4.65 GHz Hold time constraint: tccq + tcd > thold ? (30 + 25) ps > 70 ps ? No!

Fixing Hold Time Violation Timing Characteristics tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps tpd = 35 ps tcd = 25 ps Add buffers to the short paths: tpd = tcd = Setup time constraint: Tc ≥ fc = Hold time constraint: tccq + tpd > thold ?

Fixing Hold Time Violation Add buffers to the short paths: Timing Characteristics tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps tpd = 35 ps tcd = 25 ps tpd = 3 x 35 ps = 105 ps tcd = 2 x 25 ps = 50 ps Setup time constraint: Tc ≥ (50 + 105 + 60) ps = 215 ps fc = 1/Tc = 4.65 GHz Hold time constraint: tccq + tcd > thold ? (30 + 50) ps > 70 ps ? Yes!

Clock Skew The clock doesn’t arrive at all registers at the same time Skew is the difference between two clock edges Examine the worst case to guarantee that the dynamic discipline is not violated for any register – many registers in a system!

Setup Time Constraint with Clock Skew In the worst case, the CLK2 is earlier than CLK1 Tc ≥ tpcq + tpd + tsetup + tskew tpd ≤ Tc – (tpcq + tsetup + tskew)

Timing Analysis with clock skew Timing Characteristics tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps tpd = 35 ps tcd = 25 ps tskew = 50 ps tpd = 3 x 35 ps = 105 ps tcd = 25 ps Setup time constraint: Tc ≥ 265 ps fc = 1/Tc =3.77 GHz Without skew we got fc =4.65 GHz

Hold Time Constraint with Clock Skew In the worst case, CLK2 is later than CLK1 tccq + tcd > thold + tskew tcd > thold + tskew – tccq

Timing Characteristics Hold Time Violation Add buffers to the short paths: Timing Characteristics tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps tpd = 35 ps tcd = 25 ps tskew = 50 ps tpd = 3 x 35 ps = 105 ps tcd = 2 x 25 ps = 50 ps Hold time constraint: tccq + tcd > thold + tskew? (30 + 50) ps > (70 ps +50) ps ?

Timing and Retiming Retiming: Adjust the clock skew so that the clock period can be reduced. Add a few more examples on timing and retiming.

Conclusion Clock to Clock: Range of shortest and longest paths Design revision and retiming to adjust the constraints Research: Variation aware designs