1. CSE 140L Lecture 6 Interface and State Assignment Professor CK Cheng CSE Dept. UC San Diego 1

2. Interface: Quality of Input Signal Debouncers –Double-Throw Switch –Single-Throw Switch Synchronizers –Metastability –Synchronization 2

3. Debouncers: Double-Throw Switch Time 012345678 A011111111 B110101000 X110000000 Y001111111 SR debouncer 3

4. Debouncers: Single-Throw Switch Pull down V cap /V initial = e –t/RC R 2 C= -T/ln(V th /V dd ) Push up V cap /V final = 1-e -t/RC (R 1 +R 2 )C= -T/ln(1-V th /V dd ) Bounce time < T=20msec 4

5. 3- Synchronizer: Input may occur any time Asynchronous (for example, user) inputs might violate the dynamic discipline

6. Synchronizer: Metastability Metastability: A synchronizer failure that the voltage falls between 0 and 1. 6

7. 3- Metastability Any bistable device has two stable states and a metastable state between them A flip-flop has two stable states (1 and 0) and one metastable state If a flip-flop lands in the metastable state, it could stay there for an undetermined amount of time

8. 3- Flip-flop Internals Because the flip-flop has feedback, if Q is somewhere between 1 and 0, the cross-coupled gates will eventually drive the output to either rail (1 or 0, depending on which one it is closer to). A signal is considered metastable if it hasn’t resolved to 1 or 0 If a flip-flop input changes at a random time, the probability that the output Q is metastable after waiting some time, t, is: P(t res > t) = (T 0 /T c ) e -t/τ t res : time to resolve to 1 or 0 T 0, τ : properties of the circuit

9. 3- Metastability Intuitively: –T 0 /T c describes the probability that the input changes at a bad time, i.e., during the aperture time P(t res > t) = (T 0 /T c ) e -t/τ –τ is a time constant indicating how fast the flip-flop moves away from the metastable state; it is related to the delay through the cross-coupled gates in the flip-flop P(t res > t) = (T 0 /T c ) e -t/τ In short, if a flip-flop samples a metastable input, if you wait long enough (t), the output will have resolved to 1 or 0 with high probability.

10. 3- Synchronizers Asynchronous inputs (D) are inevitable (user interfaces, systems with different clocks interacting, etc.). The goal of a synchronizer is to make the probability of failure (the output Q still being metastable) low. A synchronizer cannot make the probability of failure 0.

11. 3- Synchronizer Internals A synchronizer can be built with two back-to-back flip-flops. Suppose the input D is transitioning when it is sampled by flip-flop 1, F1. The amount of time the internal signal D2 can resolve to a 1 or 0 is (T c - t setup ).

12. 3- Synchronizer: Shifter Allocate one clock cycle for logic to settle at 0 or 1. For each sample, the probability of failure of this synchronizer is: P(failure) = (T 0 /T c ) e -(T c - t setup )/τ

13. 3- Synchronizer Mean Time Before Failure If the asynchronous input changes once per second, the probability of failure per second of the synchronizer is simply P(failure). In general, if the input changes N times per second, the probability of failure per second of the synchronizer is: P(failure)/second = (NT 0 /T c ) e -(T c - t setup )/τ Thus, the synchronizer fails, on average, 1/[P(failure)/second] This is called the mean time between failures, MTBF: MTBF = 1/[P(failure)/second] = (T c /NT 0 ) e (T c - t setup )/τ

14. 3- Example Synchronizer Suppose: T c = 1/500 MHz = 2 nsτ = 200 ps T 0 = 150 pst setup = 100 ps N = 1 events per second What is the probability of failure? MTBF? P(failure) = (150 ps/2 ns) e -(1.9 ns)/200 ps = 5.6 × 10 -6 P(failure)/second = 10 × (5.6 × 10 -6 ) = 5.6 × 10 -5 / second MTBF = 1/[P(failure)/second] ≈ 5 hours

15. State Assignment Binary Code: log 2 n flip-flops for n states Gray Code: log 2 n flip-flops for n states Johnson Code: n/2 flip-flops for n states “Don’t Care” State Encoding One Hot Code: n flip-flops for n states 15

16. “Don’t Care” State Encoding State i  Q j = 0 for all j > i, Q i = 1 Q j = x for all j < i. Q n-1 Q n-2 …Q1Q1 Q0Q0 Sn-11xxxx Sn-201xxx ………… S10001x S000001 16

17. State Assignment: One Hot Code For n states, we use n flip-flops. Each state corresponds to a flip-flop. Q i = 1 iff present state = state i. Thus, one and only one flip-flop contains a “1”. We use OR gate to collect input edges. We use Mux gate to distribute the output edges. 17

18. State Assignment: One Hot s0s S0S1 S2 0 1 0 1 0 1 18

19. 3. Transformation from Mealy to Moore Machine Moore Machine: y(t) = f(x(t), s(t)) Mealy Machine:y(t) = f(s(t)) s(t+1) = g(x(t), s(t)) C1C2 CLK x(t) y(t) Mealy Machine C1C2 CLK x(t) y(t) Moore Machine s(t) 19