Using the McBSP Chapter 6 C6000 Integration Workshop Copyright © 2005 Texas Instruments. All rights reserved. Technical Training Organization T TO

Goals for Module 6… CPUEDMA RCVCHAN gBufRcv ADC DAC McBSP Rcv Xmt XMTCHAN gBufXmt + COPY We will learn how to:  Use the McBSP to communicate with an external codec  Synchronize EDMA transfers with an event  Read the position of DIP switch on the DSK Technical Training Organization T TO

Outline  McBSP Overview  EDMA Synchronization Events  DSK’s Serial Communications  Initializing McBSP & AIC23  Using the AIC23  Lab 6: Audio Pass-Thru Technical Training Organization T TO

Could this be you? That darn serial port better be able to support… AC’97 SPI T1 E1 ST-Bus MVIP IOM-2 IIS Multi-Channel u-Law/A-Law Codecs AICs Full-duplex The McBSP is an extremely capable serial port Technical Training Organization T TO

Outline  McBSP Overview  Block Diagram  Data and Frame-Sync Timing  McBSP Clock Generation  Interrupt/Event Generation Technical Training Organization T TO

McBSP Block Diagram CPU EDMA InternalBusInternalBus DXRDXR DX XSR CLKR FSR CLKX FSX CLKS RBRRBRDRRDRR 32 DR RSR Expand (optional) Compress (optional) Let’s look at some basic definitions… McBSP Control Registers SPCR RCR XCRPCR SRGR Technical Training Organization T TO

McBSP Block Diagram CPU EDMA InternalBusInternalBus DXRDXR DX XSR CLKR FSR CLKX FSX CLKS RBRRBRDRRDRR 32 DR RSR Expand (optional) Compress (optional) McBSP Control Registers SPCR RCR XCRPCR SRGR Technical Training Organization T TO

Basic Definitions - Bit, Word CLK b7b6b5b4b3b2b1b0 Word FS a1a0 Bit D  “Word” or “channel” contains #bits specified by WDLEN1 (8, 12, 16, 20, 24, 32)  “Bit” - one data bit per SP clock period SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port RWDLEN1 57 XWDLEN1 57

Basic Definitions - Frame SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port  “Frame” - contains one or multiple words w0w1w2w3w4w5w6w7 Frame Word w6w7 D FS RFRLEN XFRLEN  FRLEN1 specifies #words per frame (1-128) RWDLEN1 57 XWDLEN1 57

Outline  McBSP Overview Block Diagram Data and Frame-Sync Timing  McBSP Clock Generation  Interrupt/Event Generation Technical Training Organization T TO

CLK & FS Pins: Input or Output McBSP CLKR CLKX Input or Output?  CLK/FS can be inputs or outputs SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port CLKRMFSRM 10 FSXM 11 CLKXM 8 9 CLK/FS Mode 0: Input 1: Output FSR FSX

If You Select CLK as Output … McBSP SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port Sample Rate Generator (SRGR) CLKR CLKX Rate (SRGR) CLKSM 29 CLKSM (Internal Clock) CLKOUT1 CLKS  CLKSM: selects clock src ( CLKOUT1 or CLKS ) CLKGDV 07    CLKGDV : divide down (1-255)  CLKG = (input clock) / (1 + CLKGDV )  Max transfer rate is 100Mb/s (for most ‘C6x devices) CLKG FSR FSX

If You Select FS as Output … SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port CLKSM 29 CLKGDV 07 FSGM 28 Frame Sync Gen Mode ( FSGM ):  0 = FSX gen’d on every DXR  XSR copy McBSP Sample Rate Generator (SRGR) FSR FSX CLKR CLKX CLKSM (Internal Clock) CLKOUT1 CLKS   CLKGDV CLKG Framing FSG FWID 815 FPER 2716  1 = FSX and/or FSR gen’d by “Framing”  FPER : frame sync period (12 bits)  FWID : frame sync pulse width (8 bits)

Outline  McBSP Overview Block Diagram Data and Frame-Sync Timing McBSP Clock Generation  Interrupt/Event Generation Technical Training Organization T TO

McBSP Events/Interrupts RBRDRR SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port RRDY=1 “Ready to Read” RRDY R 1  R/XRDY displays “status” of ports:  0: not ready  1: ready to read/write McBSP0 receive transmit XRDY 17 R XSRDXR XRDY=1 “Ready for Write”

EDMA McBSP Events/Interrupts RBRDRRXSRDXR RRDY=1 XRDY=1 “Ready to Read” “Ready for Write” SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port RRDYXRDY 17 RR Chan 12 XEVT0  R/XRDY displays “status” of ports:  0: not ready  1: ready to read/write  This signal can trigger:  Interrupt to CPU  Event to EDMA CPU RINT0 XINT0 1 Chan 13 REVT0 McBSP0 receive transmit

Triggering the CPU Interrupts (R/XINT) CPU RINT XINT RRDY End of Block (RCV) New FSR (frame begin) Receive Sync Error XRDY End of Block (XMT) New FSX (frame begin) Transmit Sync Error “Trigger Event” SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port RRDY 1 XRDY 17 XINTM 2021 RINTM 4 5 XINTM RRRW

EDMA Sync Events from McBSP “Ready to Read” EDMA CODECCODEC REVT RRDY=1 DRRRBRRSRDXRXSR Receive Event (REVT)  When value reaches DRR, sync event sent to EDMA.  This can be used to trigger an EDMA transfer. SP Ctrl (SPCR) Rcv Ctrl (RCR) Xmt Ctrl (XCR) Rate (SRGR) Pin Ctrl (PCR) Serial Port XRDY=1 “Ready to Write” XEVT Transmit Event (XEVT)  Sent to EDMA when DXR is emptied (and ready to receive another value) XRDY 17 RRDY 1

Outline  McBSP Overview  EDMA Synchronization Events  DSK’s Serial Communications  Initializing McBSP & AIC23  Using the AIC 23  Lab 6: Audio Pass-Thru Technical Training Organization T TO

C6713 EDMA Channels EDMAChannelEvent Description 0DSPINTHPI to DSP interrupt 1 TINT0 Timer 0 interrupt 2 TINT1 Timer 1 interrupt 3 SD_INTEMIF SDRAM timer interrupt 4 EXT_INT4 External interrupt pin 4 5 EXT_INT5 External interrupt pin 5 6 EXT_INT6 External interrupt pin 6 7 EXT_INT7 External interrupt pin 7 8 EDMA_TCC8 9 EDMA_TCC9 10 EDMA_TCC10 11 EDMA_TCC11 12 XEVT0 McBSP0 transmit event 13 REVT0 McBSP0 receive event 14 XEVT1 McBSP1 transmit event 15 REVT1 McBSP1 receive event  Each channel is associated with a specific sync event  When a sync event is unused, that channel may still be programmed for a simple block memory-copy operation EDMA chaining Technical Training Organization T TO

EDMA Sync Events ( ER ) EDMA Channels 15 REVT1 14 XEVT DSPINT EDMA_setChannel( hMyChan ) EDMA Event Input ER XEVT1 REVT1  Previously, EDMA_setChannel() triggered an EDMA channel to run  XEVT1 & REVT1 set the appropriate bits in the Event Register (ER), rather than our code doing this manually

EDMA Sync Events ( ER ) EDMA Channels 15 REVT1 14 XEVT DSPINT EDMA_setChannel( hMyChan ) EDMA Event Input ER DSPINT XEVT1 REVT1  Previously, EDMA_setChannel() triggered an EDMA channel to run  XEVT1 & REVT1 set the appropriate bits in the Event Register (ER), rather than our code doing this manually  What if there is a sync event I don’t want the EDMA to respond to? Say, DSPINT?

EDMA Sync Events ( ER, EER )  Previously, EDMA_setChannel() triggered an EDMA channel to run  XEVT1 & REVT1 set the appropriate bits in the Event Register (ER), rather than our code doing this manually  What if there is a sync event I don’t want the EDMA to respond to? Say, DSPINT? The Event Enable Register (EER) allows event inputs to be blocked. EDMA Channels 15 REVT1 14 XEVT DSPINT EDMA_setChannel( hMyChan ) EDMA Event Input ER DSPINT XEVT1 REVT1 EER 0 = 0 EER... = 1 EER 14 = 1 EER 15 = 0 EER  Note: When setting an ER bit manually ( e.g. EDMA_setChannel), the associated EER bit is ignored by the EDMA hardware. Technical Training Organization T TO

Outline  McBSP Overview  EDMA Synchronization Events  DSK’s Serial Communications  AIC23 Codec  McBSP  AIC23  Initializing McBSP & AIC23  Using the AIC 23  Lab 6: Audio Pass-Thru Technical Training Organization T TO

Control Channel Data Channel (Left, Right)  24-bit resolution (90db SNR ADC, 100db SNR DAC)  Multiple Digital transfer widths (16-bits, 20-bits, 24-bits, 32-bits)  Programmable frequency (8K, 16K, 24K, 32K, 44.1K, 48K, 96K)  AIC23 has two serial data pins:  Input for control – reads/writes AIC23’s control registers  Bidirectional pin to transfer data to A/D and D/A converters AIC23 Codec Technical Training Organization T TO

Control Data  McBSP1 connected to program AIC23’s control registers  McBSP2 is used to transfer data to A/D and D/A converters  One McBSP could be made to handle the AIC23, but since multiple McBSP’s were available, using two made the design easier On the C6713 DSK… C6416 DSK: McBSP  Codec Interface McBSP1 McBSP2 Technical Training Organization T TO

Control Data McBSP0 McBSP1  McBSP0 connected to program AIC23’s control registers  McBSP1 is used to transfer data to A/D and D/A converters  One McBSP could be made to handle the AIC23, but since multiple McBSP’s were available, using two made the design easier C6713 DSK: McBSP  Codec Interface Technical Training Organization T TO

McBSP and the DSK McBSP0 CLKR CLKX FSR FSX DR DX AD535 codec SCLK FS RCV XMT 4.096MHz clock (on DSK) EDMA  User needs to program the McBSP to communicate with the chosen device (e.g. AD535).  Some basic options include: Frame length Word length Companding? CLK (input, output, polarity) FS (input, output, polarity) Interrupt CPU? We could use the same method as lab3 (config structure)… Let’s try something different… Clocking (direction) Technical Training Organization T TO

Outline  McBSP Overview  EDMA Synchronization Events  DSK’s Serial Communications  Initializing McBSP & AIC23  McBSP Init  Codec Init  Using the AIC 23  Lab 6: Audio Pass-Thru Technical Training Organization T TO

AIC23 Codec Control McBSP General Procedure to Initialize Codec  Since the AIC23 is connected to the McBSP, you must first initialize the McBSP, then the codec. C6416 DSK  McBSP1 used for control channel C6713 DSK  McBSP0 used for control channel 1.Setup McBSP 2.Setup Codec via McBSP SPCR RCR XCR SRGR PCR MCR DXR DRR Technical Training Organization T TO

1. McBSP Setup #include MCBSP_Handle hMcbsp0; MCBSP_Config mcbspCfgControl = { 0x , // Serial Port Control Reg. (SPCR) 0x , // Receiver Control Reg. (RCR) 0x , // Transmitter Control Reg. (XCR) 0x , // Sample-Rate Generator Reg. (SRGR) 0x , // Multichannel Control Reg. (MCR) 0x , // Receiver Channel Enable (RCER) 0x , // Transmitter Channel Enable (XCER) 0x00000A0A // Pin Control Reg. (PCR) }; void initMcBSP() { hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); MCBSP_config(hMcbsp0, &mcbspCfgControl ); MCBSP_start (hMcbsp0, MCBSP_XMIT_START | MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 100); } Let's look more closely the McBSP configuration

1. McBSP Config (a) MCBSP_Config mcbspCfgControl = { MCBSP_SPCR_RMK( MCBSP_SPCR_FREE_NO, MCBSP_SPCR_SOFT_NO, MCBSP_SPCR_FRST_YES, MCBSP_SPCR_GRST_YES, MCBSP_SPCR_XINTM_XRDY, MCBSP_SPCR_XSYNCERR_NO, MCBSP_SPCR_XRST_YES, MCBSP_SPCR_DLB_OFF, MCBSP_SPCR_RJUST_RZF, MCBSP_SPCR_CLKSTP_NODELAY, MCBSP_SPCR_DXENA_OFF, MCBSP_SPCR_RINTM_RRDY, MCBSP_SPCR_RSYNCERR_NO, MCBSP_SPCR_RRST_YES ),  Puts both transmit and rcv sides into reset upon config.  Previous slide shows config as 32-bit hex values (because it fit on 1 slide).  A better method uses _RMK macros. Improves:  Readability  Maintainability  Previous slide shows config as 32-bit hex values (because it fit on 1 slide).  A better method uses _RMK macros. Improves:  Readability  Maintainability Technical Training Organization T TO

1. McBSP Config (b) MCBSP_RCR_DEFAULT, MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_SINGLE, MCBSP_XCR_XFRLEN2_OF(0), MCBSP_XCR_XWDLEN2_8BIT, MCBSP_XCR_XCOMPAND_MSB, MCBSP_XCR_XFIG_NO, MCBSP_XCR_XDATDLY_0BIT, MCBSP_XCR_XFRLEN1_OF(0), MCBSP_XCR_XWDLEN1_16BIT, MCBSP_XCR_XWDREVRS_DISABLE ),  Default values provided in CSL for each register (or bit) Technical Training Organization T TO

1. McBSP Config (c) MCBSP_SRGR_RMK( MCBSP_SRGR_GSYNC_FREE, MCBSP_SRGR_CLKSP_RISING, MCBSP_SRGR_CLKSM_INTERNAL, MCBSP_SRGR_FSGM_DXR2XSR, MCBSP_SRGR_FPER_OF(0), MCBSP_SRGR_FWID_OF(19), MCBSP_SRGR_CLKGDV_OF(99) ), Technical Training Organization T TO

1. McBSP Config (d) MCBSP_MCR_DEFAULT, MCBSP_RCERE0_DEFAULT, MCBSP_RCERE1_DEFAULT, MCBSP_RCERE2_DEFAULT, MCBSP_RCERE3_DEFAULT, MCBSP_XCERE0_DEFAULT, MCBSP_XCERE1_DEFAULT, MCBSP_XCERE2_DEFAULT, MCBSP_XCERE3_DEFAULT,  These registers control the multi-channel capabilities of the McBSP.  We aren’t using these features in our lab exercises.  These registers control the multi-channel capabilities of the McBSP.  We aren’t using these features in our lab exercises. Technical Training Organization T TO

1. McBSP Config (e) MCBSP_PCR_RMK( MCBSP_PCR_XIOEN_SP, MCBSP_PCR_RIOEN_SP, MCBSP_PCR_FSXM_INTERNAL, MCBSP_PCR_FSRM_EXTERNAL, MCBSP_PCR_CLKXM_OUTPUT, MCBSP_PCR_CLKRM_INPUT, MCBSP_PCR_CLKSSTAT_DEFAULT, MCBSP_PCR_DXSTAT_DEFAULT, MCBSP_PCR_FSXP_ACTIVELOW, MCBSP_PCR_FSRP_DEFAULT, MCBSP_PCR_CLKXP_FALLING, MCBSP_PCR_CLKRP_DEFAULT ) }; Technical Training Organization T TO

Codec Initialization Specify codec configuration void initCodec(MCBSP_Handle hMcbsp) { short codecConfig[10] = { 0x0017, // 0 Left line input channel volume 0x0017, // 1 Right line input channel volume 0x01f9, // 2 Left channel headphone volume … }; for (i = 0; i < 10; i++) { … MCBSP_write(hMcbsp,(i << 9)|codecConfig[i]);} } AIC23 Codec Control McBSP 1.Setup McBSP 2.Setup Codec via McBSP SPCR RCR XCR SRGR PCR MCR DXR DRR Write init values to codec

Outline  McBSP Overview  EDMA Synchronization Events  DSK’s Serial Communications  Initializing McBSP & AIC23  Using the AIC23 ( setup EDMA )  Lab 6: Audio Pass-thru Technical Training Organization T TO

McBSP Using the Codec (via EDMA) gBufXmt EDMA Chan DXR XEVT2 (… EDMA_OPT_SUM_INC,// Src update mode? EDMA_OPT_DUM_NONE,// Dest update mode? EDMA_OPT_TCINT_YES, // Cause EDMA interrupt? EDMA_OPT_TCC_OF(0),// Transfer complete code? EDMA_OPT_FS_NO),// Use frame sync? … EDMA_SRC_OF(gBufXmt), // src address? EDMA_DST_OF(0), … // dest address? hEdmaXmt = EDMA_open ( EDMA_CHA_XEVT2, EDMA_OPEN_RESET); gEdmaConfigXmt.dst = MCBSP_getXmtAddr(hMcbsp2); EDMA_intEnable(gTcc); Note: McBSP1 and XEVT1 for C6713 Technical Training Organization T TO

Outline  McBSP Overview  EDMA Synchronization Events  DSK’s Serial Communications  Initializing McBSP & AIC23  Using the AIC 23  Lab 6: Audio Pass-thru Technical Training Organization T TO

Lab 6 – Audio Pass Thru CPUEDMA RCVCHAN gBufRcv ADC DAC McBSP Rcv Xmt XMTCHAN gBufXmt + COPY Goals: 1.EDMA (RCV) copies values from DRR to gBufRcv 2.CPU copies gBufRcv to gBufXmt 3.EDMA (XMT) copies gBufXmt to DXR 4.Opt: add sine to gBufRcv based on DIP switch Technical Training Organization T TO

Lab 6 Debrief Technical Training Organization T TO

Chapter 6: Optional Topic  DMA Synchronization and DMA Split Mode Click Here for Chapter 7 Channel Sorting Technical Training Organization T TO

DMA Synchronization Primary Ctrl Secondary Ctrl Source Destination Xfr Count DMA 01 STARTDSTDIR 76 SRCDIR 5498 ESIZE 13 INDEX (Src: mem_8) bit Pixels DMA D/A  Is the DAC as fast as the EDMA? No, the EDMA needs to be sync’d up to the DAC.  Unlike the EDMA, any DMA channel can be sync’d to and EDMA event. DSTDIR 00 EXT_INT 4 “Next” DMA Sync Events None (default) TINT TINT EXT_INT4... (see periph guide) 2319 WSYNC RSYNC Technical Training Organization T TO

Frame Synchronization 01 START 2319 WSYNC 1814 RSYNC 26 FS FS (Frame Sync) 0: NO (no Frame Sync) 1: YES (use Frame Sync) Move whole frame on sync event FS (Frame Sync) 0: NO (no Frame Sync) 1: YES (use Frame Sync) Move whole frame on sync event  Similar to FS on the EDMA  Unlike the EDMA, though, there is not block-level (2D) synchronization Technical Training Organization T TO

018C_0000 DMA Split Mode Primary Ctrl Secondary Ctrl Source Destination Xfr Count DMA Primary Ctrl SPLIT  4 addresses are needed when handling receive & transmit parts of a serial port, unfortunately the DMA only has two address registers. This is solved by: 1. Select SPLIT mode in Primary Control Register 2. Source/Destination registers contain the From/To memory addresses 3. Use global reg (A, B, or C) for address of McBSP’s DRR register. DMA split mode knows to find the DXR address in the next word location.  Split mode allows one DMA Channel to handle both rcv/xmt DRR DXR Split SRC Split DST (018C_0004) RSYNC WSYNC Destination Source DMA CHx Xfr Count Split Mode: 00 Split Disabled 01 Use Global Address Reg A 10 Use Global Address Reg B 11 Use Global Address Reg C DMA Global Register A Technical Training Organization T TO

DMA / EDMA Comparison Features: DMAC67x EDMAC64x EDMA Channels 4 channels + 1 for HPI 16 channels + 1 for HPI + Q-DMA 64 channels + 1 for HPI + Q-DMA Sync  element  frame  element  frame  2D (block) Sync Events Any channel can use any event Each channel has specific event CPU Interrupts 41 Interrupt Conditions six:  3 for Count  3 for errors Count = 0 Reload (Auto-Init)~26921 Chain Channels None4 channels (8-11)64 channels Priority 4 fixed levels2 prog levels4 prog levels McBSP Operation Split ModeUses two EDMA channels

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