Basic terminology associated with counters Technician Series ©Paul Godin Updated Jan 2015

Introduction Counters are part of a family called Sequential Circuits. Sequential circuits provide predictable output patterns. Sequential circuits are used in many applications, including: digital counting counting up or down arithmetic operations control circuits frequency dividers clocks timing circuits...

Introduction Basically, counters are devices that are able to count clock pulses. Counters are constructed from Flip-Flops Available as counter ICs Sn74LS192 Up/Down 4-bit counter with preset and clear

Digit Significance 10110 MSB LSB Most Significant Bit (MSB): This bit occupies the position with the greatest numerical value in a binary number, and is the left-most bit in a binary number. Least Significant Bit (LSB): This bit occupies the position with the smallest numerical value in a binary number, and is the right-most bit in a binary number. When looking at counter outputs it is important to remember which is the MSB and which is the LSB. Example: 10110 MSB LSB

Modulus The Modulus of a counter refers to the number of unique output states it can produce. Also referred to as “MOD”. Example: a counter counts in the following sequence: 000, 001, 010, 011, then back to 000 The modulus of this counter is 4. It has 4 unique output states (including zero).

Maximum Modulus The maximum modulus of a counter is 2N, where ‘2’ indicates the number of possible bit states (1 or 0), and ‘N’ represents the maximum number of bits. The maximum modulus of a 3-bit counter is 8. There are 8 unique output states (from 000 to 111). What is the maximum modulus of a 5 bit counter?

Counter Sequences A Bit is a single binary digit (1 or 0). A binary number is comprised of multiple bits. Full Sequence Count refers to a natural count that includes all possible binary numbers. It’s modulus is the same as its maximum modulus. A Truncated Sequence Count is when the modulus is less than its maximum, or where less than all possible binary numbers are used.

Sequential Circuit Counter states are sequential. An output state will follow another in a sequence. State Diagrams are used to visually represent the sequence of these states. 000 001 010 011 100 State Diagram of a truncated sequence

Sequential Circuits Counters normally recycle or restart their sequence. Example: 000 001 010 011 100 101 110 111

Up/Down UP DOWN A natural count can be Up or Down: 000 001 010 011 100 101 110 111 UP DOWN

Returns to the first state. State Table A State Table is another means of presenting state sequences. As with the state diagram, the state table determines the next output based on the present output state. Current Next QC QB QA 1 Returns to the first state. State Table

Review Questions A truncated mod-6 3-bit up counter has a starting point of all low outputs. Draw the state diagram Draw the state table If a full sequence down counter has a current output of 0101, what is the next output? If a counter requires a modulus of 130, what is the minimum number of bits required?

Asynchronous Counters

Binary Counting 1 ↓ If one looks at the changes in individual bits of a binary count from one value to the next, a frequency pattern emerges.

Binary Counting 1 ½ f ¼ f f 1 ↓ Each more significant digit has half the frequency of the previous digit. A divide-by-two frequency divider can be used to build a counter.

Frequency Division Q J T Clk Clk 1 K Q A device that divides the input frequency by 2 is a toggling JK flip-Flop J K Q Clk 1 Clk Q T

Asynchronous Counter To count in binary, the frequency of each more significant bit needs to divide the previous bit’s frequency by 2.

Note the labeling standard for counters. 4-bit Binary Counter Note the labeling standard for counters. The LSB is always “A”

Asynchronous The counter bits are not clocked in synchronization; the source is applied to the first flip-flop only. This counter design is therefore asynchronous (not synchronous). It takes time for the clock edge to work its way through each flip-flop. Propagation delay is the cause of this effect. Because of the output pattern where the edge works its way through each flip-flop, asynchronous counters are also known as Ripple Counters.

Timing Diagrams It is important to remember to look at the state of the inputs just before the edge when drawing timing diagrams. When looking at the timing diagram, remember to identify the MSB and the LSB. The LSB is the Flip-Flop closest to the external clock input.

Reading a Counter Timing Diagram 1 LSB MSB Based on the observed pattern, the least significant bit (LSB) is represented at the top of the timing diagram and the MBB is at the bottom. The values must be read from the bottom up (MSB to LSB).

Truncating Truncating is when a counter is prevented from reaching its maximum modulus. For example, a 3-bit mod-5 counter will have 5 unique states but will not have the maximum modulus of 23, or mod-8. 000 001 010 011 100 Values 101, 110 and 111 are not included in this sequence

Truncating Method The most common method of truncating a count is to: Detect the presence of the first unwanted value using logic gates Immediately reset or preset the counter back to the desired starting state

Truncating Method 101 Immediate Reset Next natural state 000 100 001 The time from detection to an immediate reset is the time it takes for a signal to travel through the logic gates (nanoseconds). 011 010

Truncating Circuit Detect 101 Counter Reset all

Truncating circuit in EWB

Frequency Division A typical application for asynchronous counters is frequency division. Example: Use a 60 Hz source to supply 1 pulse per second (1 pps) Mod-6 10Hz Mod-10 60Hz 1Hz

Frequency Division Mod-6 QC Mod-10 QD 1Hz 60Hz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 000 001 010 011 100 101 DCBA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 CBA 000 001 010 011 100 101 Note the MSB has a frequency of 1/6th the input frequency (at 33% Duty Cycle) Note the MSB has a frequency of 1/10th the input frequency (at 20% Duty Cycle)

Count Direction To reverse the count direction of an asynchronous counter, the following 3 circuit changes can be applied: Change the clocking edge with a different Flip-Flop Change Q to Q’ in the design Complement the output (use the Q/Q’ output) Note that making two changes (reversing the direction twice) will revert back to the original direction.

END ©prgodin @ gmail.com Updated Jan 2015