CDCA 2203 Class 3 Prepared by: Eng Kok Siong Copyright 2010 All Rights Reserved Elements of Computer Architecture Open University Malaysia

CDCA 2203 Elements of Computer ArchitectureSlide 2 Topic 7: PC Organization The earlier version of IBM PC Invented around The most popular IBM PC was invented a few years after that. It was known as the PBM PC/XT (XT refers to Extra Technology) which used the Intel 8086 microprocessor. Later, when Intel produced the microprocessor chip, the IBM PC was improved to a IBM PC/AT (AT refers to Advance Technology).

CDCA 2203 Elements of Computer ArchitectureSlide 3 IBM PC Bus

CDCA 2203 Elements of Computer ArchitectureSlide 4 The Next IBM PC IBM planned to produce a higher-powered microcomputer compared to the PC, known as PS/2. The PS/2 was better designed compared to the PC. However, computer users became so accustomed with the PC that the PS/2 project became a failure. The failure of PS/2 brought focus back to IBM PC. The next move was to enhance and increase the capabilities of the PC by using high-powered microprocessors such as the 80386, followed by the and later Pentium. A smaller computer that required only a motherboard was then invented. This type of computer is known as Laptop or Notebook. Further progress came about with the usage of compact disc as storage device and enabled the PC to progress into a multimedia computer.

CDCA 2203 Elements of Computer ArchitectureSlide 5 Changes in the Bus System In order to conduct a 32-bit data provided by a particular microprocessor, the new PC used a bus system known as the EISA (Extended Industry Standard Architecture). Later, another system bus, VESA (Video Electronics Standard Association) was introduced to connect the disc and monitor directly to the microprocessor. Another type of bus used by the PC was the SCSI (Small Computer System Interface), which was read as “skuzzy”. SCSI was accepted as a standard by ANSI (American National Standard Institute) in The bus connects I/O devices such as the hard disc unit and printer to the PC. The new bus system set for computers is based on Pentium and known as PCI (Peripheral Control Interface). PCI provides 32 bus or 64 bit.

CDCA 2203 Elements of Computer ArchitectureSlide 6

CDCA 2203 Elements of Computer ArchitectureSlide 7 Topic 7: RISC Machines Architecture of the RISC or Reduced Instruction Set Computing machine

CDCA 2203 Elements of Computer ArchitectureSlide 8 Chips that are based on old technology are known as the CISC or Complex Instruction Set Computing. The development of technology has narrowed the gap between the RISC and CISC. This is because the cost of producing microprocessor chips are becoming lower as most CISC chips come together with RISC’s instructions, and the new RISC has the same instructions as the older version. This appears as if there is a correlation between these two microprocessors. The rapid growth in the high-level language led to the development of a language that has constructions such as if, while, and case. This caused a semantic gap between the high-level language and the machine language, which was troublesome for writing compiler. As such, the machine language level was increased to narrow the semantic gap.

CDCA 2203 Elements of Computer ArchitectureSlide 9 RISC architecture is based on a few principles as follow: Single instruction for each data execution cycle Load/save architecture No micro codes Fixed format instructions Small Number of Instructions Put complexity in compiler RISC Architecture

CDCA 2203 Elements of Computer ArchitectureSlide 10 To achieve the principle stated above, there are five important steps in designing a RISC machine: 1. As RISC machines involve reduced instructions, thus any application that uses this particular machine need to be analyzed carefully to determine the type of main operation that needs to be provided. 2. Design an optimal data path for the particular main operation. 3. Design instructions that form the main operation by using that particular data path. 4. Increase new instruction only if it is does not cause delay in a machine. 5. Repeat this process for other resources such as cache memory, main memory and co-processor arithmetic.

CDCA 2203 Elements of Computer ArchitectureSlide 11 RISC designers were concerned with the way they were going to invent a high speed chip. As such, the pipelining concept was used as one of the best methods to invent this chip. One of the issues raised during the execution of pipelining was the speed of the memory. This problem was solved using the cache memory. Pipelining

CDCA 2203 Elements of Computer ArchitectureSlide 12

CDCA 2203 Elements of Computer ArchitectureSlide 13

CDCA 2203 Elements of Computer ArchitectureSlide 14 Register Usage To enable instruction to be executed in a single data path cycle, the RISC compiler uses many registers to reduce the transfer of data from the memory. Registers in RISC 1 is divided into 4 groups with each group having 8 registers: 1.The first group holds global registers and indicators. It is not specified to any instruction but is used by most of the instructions throughout a program. 2.The second group holds the entry parameters for an instruction. 3.The third group is used for local variables. If the number of local variables exceeds eight, it will be stored in a stack in the main memory. 4.The fourth group is used for the exit parameters.

CDCA 2203 Elements of Computer ArchitectureSlide 15 Advantages of RISC

CDCA 2203 Elements of Computer ArchitectureSlide 16 Disadvantages of RISC 1.Quality of the Instruction code RISC processor's capability depends on the code that will be executed. If the compiler fails to do its job, the processor will take more time to execute the instruction. 2.Increasing size of code RISC needs many instructions to complete a single task. Therefore, the size of the code will become a problem. 3.System design Another problem is that RISC needs high-speed memory system to receive instructions. The RISC usually has many cache memory.

CDCA 2203 Elements of Computer ArchitectureSlide 17 Discussion Briefly describe and summarize the CPU. There are two main desktop CPU manufacturers, they are Intel and AMD. Both of these companies have a power CPU and a Budget CPU. 1.The Power CPU's are the Core 2 Quad from Intel and the Phenom X3 and Phenom Quad from AMD. 2.The budget CPU's are the Celeron from Intel and the Sempron from AMD. Price is a big factor between these CPU's. Check the latest prices of these CPU's below. 3.The CPU's speed is a measure of MHz (megahertz) or more recently GHz (gigahertz). A chip with a megahertz rating of 900Mhz would be able to complete 900Million cycles every second.

CDCA 2203 Elements of Computer ArchitectureSlide 18 Discussion Briefly describe and summarize the system memory. RAM SRAM retains its contents as long as electrical power is applied to the chip. DRAM, on the other hand, has an extremely short data lifetime-typically about four milliseconds. Hybrid Hybrid memories can be read and written as desired, like RAM, but maintain their contents without electrical power, just like ROM. ROM The very first ROMs were hardwired devices that contained a preprogrammed set of data or instructions. The contents of the ROM had to be specified before chip production, so the actual data could be used to arrange the transistors inside the chip.

CDCA 2203 Elements of Computer ArchitectureSlide 19 Topic 9: Machine Language Instructions Programming Model Components

CDCA 2203 Elements of Computer ArchitectureSlide 20 Register is a component that stores information that will be processed by an instruction that is currently being executed. Registers are classified into few types: 1.Program Counter (PC) are registers that indicate the address of the instruction to be executed 2.Accumulator (AC) are registers that store arithmetic results arithmetic. 3.Flags or Program Status Word (PSW) is a group of a few bits with each bit storing the status of a particular operation. 4.General Register can be used to store data during the execution of an operation. Register

CDCA 2203 Elements of Computer ArchitectureSlide 21 Memory Location

CDCA 2203 Elements of Computer ArchitectureSlide 22 Stacks The lowest location in the stack has a permanent address. The lowest location of the stack is at 4020 and the highest location of the stack is indicated by SP is Stacks normally expand from the highest order of memory address to the lowest memory address.

CDCA 2203 Elements of Computer ArchitectureSlide 23 Two main operations in stack are PUSH X and POP Y. 1.PUSH X moves the SP to the front by reducing the stack pointer’s value and then putting X into the memory location as indicated by SP. Then, the PUSH adds one element to the size of the stack. 2.POP Y reduces the size of the stack by keeping the highest element in Y and then extracts it from the stack by adding the pointer’s value according to the size of element that has been extracted.

CDCA 2203 Elements of Computer ArchitectureSlide 24 I/O Devices I/O devices connected to the CPU are devices that are visible to the programmer of the machine language. To perform the input or output operation, the programmer has to directly control all these devices.

CDCA 2203 Elements of Computer ArchitectureSlide 25 A machine language program consists of a set of instructions that specifies an action. As the machine at this level is only able to read binary numbers, all the instructions must be written in the binary numbering system. This numbering system will determine the instruction that the machine has to execute. The machine language instruction can be classified as shown below: 1.Data Movement Instruction 2.Arithmetic and Logic Instruction 3.Comparison and Conditional Jump 4.Subroutine Call Instruction 5.Input and Output Instructions

CDCA 2203 Elements of Computer ArchitectureSlide 26 Generally, the instructions are taken from the memory location in a sequential manner. However, there are situations whereby instructions are taken from other memory locations. These situations are: 1.Due to the conditional jump 2.Subroutine calls cause the instructions at beginning of a program to be executed. 3.Interrupts Control Flow

CDCA 2203 Elements of Computer ArchitectureSlide 27 Since machine language uses binary codes, all instructions and data must be encoded into binary systems. Each instruction has an operation code or Opcode that states the action that should be executed. Instruction Format Addressing can be divided into 4 modes as follow: 1.Immediate addressing 2.Direct addressing 3.Register Addressing 4.Indirect Addressing

CDCA 2203 Elements of Computer ArchitectureSlide 28 There are four different I/O schemes that can be used: 1.Programmed I/O This microcomputer has one instruction for each input and output known as IN and OUT instruction. 2.Controlled-Interrupt I/O The weakness of the Programmed I/O method is it spends most of the time circulating in loops, waiting for the device to be ready. This situation is known as Busy Waiting. 3.DMA I/O The solution for the problems above is by going back to Programmed I/O method but using a new chip known as DMA. 4.Channel I/O Things are different at the Mainframe. Normally, this machine deals with many I/O operations. This machine uses a special I/O processor known as channel. Input / Output