1. Today’s agenda Hardware architecture and runtime system
Additional slides
Module-3
Lab1 will be released soon
System calls: create(),resume(),kill(), wait(), signal(), sleep(), sleepms(), …
Read Chapter 1-2
Producer-consumer sample in chapter 2
CS354-Fall2018

2. CS250 in 15 minutes
CS354-Fall2018

3. Processors Each CPU has a specific set of instructions
All CPUs contain
General registers inside to hold key variables and temporary results
Special registers visible to the programmer
Program counter contains the memory address of the next instruction to be fetched
Stack pointer points to the top of the current stack in memory
Control registers (e.g., CR0-CR4 in x86)
PSW (Program Status Word) contains the condition code bits which are set by comparison instructions, the CPU priority, the mode (user or kernel) and various other control bits.
CS354-Fall2018

4. How Processors Work Execute instructions CPU cycles Two modes of CPU
Fetch (from mem)  decode  execute
Program counter (PC)
When is PC changed?
Pipeline: fetch n+2 while decode n+1 while execute n
Two modes of CPU
User mode (a subset of instructions)
Privileged mode (all instruction)
Trap (special instruction)
CS354-Fall2018

5. Memory Access Memory read: How many mem access for one instruction?
Assert address on address lines
Wait till data appear on data line
Much slower than CPU!
How many mem access for one instruction?
Fetch instruction
Fetch operand (0, 1 or 2)
Write results (0 or 1)
How to speed up instruction execution?
CS354-Fall2018

6. Memory-Storage Hierarchy
<
- 4MB
-1GB
-TB
-TB
CS354-Fall2018

7. Memory Registers internal to CPU (as fast as CPU)
Storage 32x32 bits on a 32-bit CPU, 64x64 on 64 bit CPU (less than 1KB in both cases)
Cache memory controlled by hardware
Cache hit and miss
RAM (Random Access Memory)
Disk (magnetic disk), CD-ROM, DVD,…
Cylinder, track, …
Non-volatile Memory
ROM (Read Only Memory)
Programmed at the factory and can’t be changed
EEPROM (Electrically Erasable ROM)
Flash RAM
Can be erased and re-written
Volatile Memory
CMOS holds current time and date

8. CPU Cache Cache hit: Cache miss: no need to access memory
data obtained from mem, possibly update cache
CS354-Fall2018

9. Memory Management How to protect programs from each other?
How to handle relocation ?
Base register
Limit register
Check and Mapping of Addresses
Virtual Address - Physical Address
Memory Management Unit (MMU – located on CPU chip or close to it
Performance effects on memory system
Cache
Context switch

10. I/O Devices Controller Device Example: Disk Controller
Controllers are complex converting OS request into device parameters
Controllers often contain small embedded computers
Device
Fairly simple interfaces and standardized
IDE (Integrated Drive Electronics) – standard disk type on Pentiums and other computers

11. I/O Devices Device Driver
Needed since each type of controller may be different.
Software that talks to a controller, giving it comments and accepting responses
Each controller manufacturer supplies a driver for each OS it supports (e.g., drivers for Windows XP, Longhorn, UNIX)

12. Methods for I/O How device driver talks to controller Busy wait
Interrupt
DMA

13. Bus Pentium systems have eight buses
Cache, local, memory, PCI, SCSI, USB, IDE, ISA
PCI (Peripheral Component Interconnect) bus is successor to IBM PC ISA bus
Intel bus, 528MB/sec
ISA (Industry Standard Architecture) bus
16.67 MB/sec
Specialized buses:
SCSI (Small Computer System Interface)
160MB/sec – for disks, scanners (popular on Macintosh, UNIX)
USB (Universal Serial Bus)
1.5 MB/sec
IEEE 1394 – FireWire (Apple) bus
50MB/sec, connectivity for cameras to computer
IDE (Integrated Drive Electronics) bus
Disk, CD-ROM

14. Structure of an Intel Pentium System