Adapted from Computer Organization and Design, Patterson & Hennessy, UCB ECE232: Hardware Organization and Design Part 5: MIPS Instructions I

ECE232: MIPS Instructions-I 2 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Computer Organization  5 classic components of any computer  We have looked at datapaths (adder, multiplier, …) Processor (CPU) (active) Computer Control (“brain”) Datapath Memory (passive) (where programs, & data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk (where programs, & data live when not running)

ECE232: MIPS Instructions-I 3 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Instruction Set Architecture (ISA)  Key Idea: abstraction hide unnecessary implementation details helps us cope with enormous complexity of real systems I/O systemProcessor Compiler Operating System (Unix; Windows) Application (FireFox) Digital Design Circuit Design Instruction Set Architecture Datapath & Control transistors, IC layout Memory Hardware Software Assembler

ECE232: MIPS Instructions-I 4 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren The Instruction Set: a Critical Interface instruction set software hardware The actual programmer visible hardware view

ECE232: MIPS Instructions-I 5 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Von Neumann Computer  Stored Program Concept A instruction is a string of bits A program is written as a sequence of instructions Instructions are stored in a memory They are read one by one, decoded and executed Also called Von Neumann Computer after the inventor of the stored program concept  The First Von Neumann Computer was built at the University of Manchester in 1948 Vacuum Tube Magnetic Drum Memory

ECE232: MIPS Instructions-I 6 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction

ECE232: MIPS Instructions-I 7 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Processor Design Levels  Architecture (ISA) programmer/compiler view “functional appearance to its immediate user/system programmer” Opcodes, addressing modes, architecture registers  Implementation (µ-architecture) processor designer view “logical structure or organization that performs the architecture” Pipelining, functional units, caches, physical registers  VLSI Realization (chip) chip designer view “physical structure that embodies the implementation” Gates, cells, transistors, wires

ECE232: MIPS Instructions-I 8 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Distinct Three Levels  Processors having identical ISA may be very different in organization. Intel and AMD  Processors with identical ISA and identical organization may still be different Different cache size Different clock frequency  Language of the Machine  MIPS instruction set architecture similar to other architectures developed since the 1980's used by NEC, Nintendo, Silicon Graphics, Sony Design goals: maximize performance and minimize cost - reduce design time Chapter 2: Instructions

ECE232: MIPS Instructions-I 9 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Program View of Memory  Memory viewed as a large, single -dimension array, with an address  A memory address is an index into array  The index points to a byte of memory - "Byte addressing"  A 32-bit machine addresses memory by a 32-bit address  Access bytes (8 bits), words (32 bits) or half-words Processor (CPU) Computer Control Datapath Memory Devices Input Output bits of data  ?

ECE232: MIPS Instructions-I 10 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Memory – word addressing Memory 4GB Max (Typically 512MB-2GB) 0x x x x C 0x x x x C 0xfffffff4 0xfffffffc CPU Address Bus Word 0 (bytes 0 to 3) Word 1 (bytes 4 to 7) Memory  Every word in memory has an address  Today machines address memory as bytes, hence word addresses differ by 4 Memory[0], Memory[4], Memory[8], … Called the “address” of a word

ECE232: MIPS Instructions-I 11 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Memory Addressing  Questions for design of ISA Read a 32-bit word as four loads of bytes from sequential byte addresses or as one load word from a single byte address? One load How do byte addresses map onto words? Start from MS (Most Significant) byte or LS byte Can a word be placed on any byte boundary? MIPS: No Aligned Not Aligned Alignment: require that objects fall on address that is multiple of their size.

ECE232: MIPS Instructions-I 12 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Addressing words: Big or Small Endian  Big Endian: address of most significant byte = word address (xx00 = Big End of word) IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA  Little Endian: address of least significant byte = word address (xx00 = Little End of word) Intel 80x86, DEC Vax, DEC Alpha msblsb little endian byte big endian byte 0

ECE232: MIPS Instructions-I 13 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Registers  Once a memory is fetched, the data must be placed somewhere in CPU  Advantages of registers registers are faster than memory registers can hold variables and intermediate results memory traffic is reduced, so program runs faster code density improves (later) Processor (CPU) Computer Control Datapath Registers Memory Devices Input Output

ECE232: MIPS Instructions-I 14 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Registers  code for A = B + C (This is not MIPS code, It is in English) load R1,B # R1 = B load R2,C # R2 = C add R3,R1,R2 # R3 = R1+R2 store R3,A # A = R3  Early ISAs supported a few registers (8 or less) (Intel’s X86)  Many current processors support 32 registers (MIPS)  The more registers available, the fewer memory accesses will be necessary Registers can hold lots of intermediate values  Instructions must include bits to specify which registers to operate on register address

ECE232: MIPS Instructions-I 15 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Typical Operations (little change since 1960) Data MovementLoad (from memory) Store (to memory) register-to-register move input (from I/O device) output (to I/O device) push, pop (to/from stack) Arithmeticinteger (binary + decimal) or FP Add, Subtract, Multiply, Divide Logicalnot, and, or, set, clear Shiftshift left/right, rotate left/right Control (Jump/Branch)unconditional, conditional Subroutine Linkagecall, return Interrupttrap, return Graphics (MMX)parallel subword ops (e.g., 4-16 bit add)

ECE232: MIPS Instructions-I 16 Adapted from Computer Organization and Design, Patterson&Hennessy,UCB, Kundu,UMass Koren Top 10 80x86 Instructions RankinstructionAverage Percent executed 1load22% 2conditional branch20% 3compare16% 4store12% 5add8% 6and6% 7sub5% 8move register-register4% 9call1% 10return1% Total96% ° Simple instructions dominate instruction frequency While theoretically we can talk about complicated addressing modes and instructions, the ones we actually use in programs are the simple ones => RISC philosophy