1. Implementation of a Stored Program Computer ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides2.ppt Modification date: Oct 16, 2014 1

2. Component Parts of a Stored Program Computer Consists of: Processor Memory Input circuits and devices Output circuits and devices Input devices (such as a keyboard) used to enter information. Output devices (such as a printer) used to obtain results from the computer. 2

3. Internal Structure of Computer Convenient to connect the processor, main memory and I/O connect through a set of common wires called a “bus”: Bus (set of wires) Input device(s)Output devices InputMain Processor Output interface(s)memoryinterface(s) Instructions and data Note: Recent computers use more than one bus – separate buses for memory etc. 3

4. Processor fetches binary encoded machine instructions from memory and performs actions defined, for example, add two numbers together and put result back in memory. Data needed for the calculation also stored in memory. 4 Main memory Set of storage locations holding binary patterns. Used to hold both machine instructions and data

5. 5 Memory Addressing Each location given a unique address (a binary number starting from zero). Each “addressable” location holds a fixed number of bits. Any location can be accessed at high speed in any order (random access memory).

6. 6 Size of memory locations In the early days of computers (and perhaps up to 1970), each manufacturer decided on how many bits would be in each memory location. Various sizes existed e.g. 24 bits, 36 bits, 40 bits, etc. Usually dictated by the number of bits in the instruction. Also defined the number of bits in numbers stored in memory. Currently (and for last 30 years at least), each addressable memory location holds 8 bits (a byte) Originally convenient for holding ASCII (American Standard Code for Information Interchange) code that represented alphanumeric characters (letters, digits, symbols as found on a keyboard). More recently Unicode/UTF-8 variable width encoding (1 - 4 bytes) encoding mostly used - Encodes most of characters used in world (ASCII a subset). See www.unicode.org/, en.wikipedia.org/wiki/UTF-8www.unicode.org/

7. 7 Size of memory locations continued Eight bits is not large enough for encoding machine instructions or most numbers. For more than eight bits, consecutive locations used. Address given by address of first location. Example 32-bit integer variables a, b, c, and d might be located at addresses 0, 4, 8, 12. Little Endian - Least significant byte stored in first location (little end) or Big Endian - Most significant byte stored first location, (big end) depending upon convention of processor: Big endian – early common approach Found in some current processors Used in network protocols Intel uses little endian (a little easier logic) Little endian/big endian from Gulliver’s Travels 0 4 8 12

8. 8 Little endian (little end first) Big endian (big end first)

9. 9 Question Suppose a compiler uses the memory locations starting from location zero to hold the variable x using big endian representation. Specify what would be in these memory locations (in binary) if the program has the statement: int x = 17; The memory is byte-addressable (each location holding a byte) and x is a 32-bit number. Answer

10. 10 Follow-on question Suppose x is then read from memory by a processor using little endian representation. What value would it get? Answer

11. 11 Bytes, half word, words, double words and all that Many processors support multiple data sizes: High level language declaration of variable x 8 bits byte byte x; (Java ) char x; (C) 16 bits half words 32 bits wordsint x; 64 bits double wordslong int x; Other formats also (floating point).

12. 12 Machine Instructions The operation of an instruction reduced to a very simple form. Consider a calculation one might write in a high level language: x = (y + z) / (a - b); where a, b, x, y, and z are declared as integers. Unreasonable to provide a specific machine instruction just for this calculation. Need to break down calculation into a series of simple arithmetic operations.

13. 13 Suppose the variables a, b, x, y, and z are stored by the compiler in memory locations 100, 104, 108, 112, and 116: temp1 = y + z temp2 = a - b x = temp1/temp2 temp1, temp2 could be memory locations but better to use fast internal register storage, see later. Note: integers are stored in registers by the compiler if possible

14. 14 Machine Instructions Each of the steps in the previous example: temp1 = y + z temp2 = a - b x = temp1/temp2 might be encoded into one machine instruction. Each machine instruction usually only has one operation (+, - etc), possibly two source operands, and a single result.

15. 15 Machine Instruction Encoding A binary pattern that specifies one operation (usually), the operands used for the operation and where the result should be placed if any.

16. 16 Op-code Encoding Suppose there were 60 different operations, add subtract, multiply, divide, etc. Six bits would be sufficient (2 5 <= 60 < 2 6 ). Could allocate one pattern for each operation: Example op-code ADD (“ADD”) 000001 SUBTRACT (“SUB”) 000010 MULTIPLY (“MUL”) 000011 DIVIDE (“DIV”) 000100 etc... Sometimes more complex encoding used. Many possibilities. Pattern of all zeros often reserved for no operation (“no-op”)

17. 17 Specifying the Locations of Operands First let us assume operands and results in main memory: Three-Address Format Note Order of operands here is with destination first but it could be different depending upon processor.

18. 18 Example: Addition

19. 19 Machine Instruction The processor executes machine instructions which are binary patterns. The previous machine instruction might be encoded as: where in this case, 6 bits in opcode and 32 bits for each address.

20. 20 Assembly Language and Machine Instructions Much more convenient to use an “assembly language” notation to describe machine instruction rather than actual binary patterns. Previous machine instruction might be written in assembly language as: ADD [300], [200], [100] where [ ] means “contents of memory”, a common notation. ADD is the op-code mnemonic.

21. 21 The 3-(memory) address format has the disadvantages: Long instruction length Three memory accesses and rarely used.

22. 22 Two-Address Format Operands and results in memory. One operand and result same location Eliminates one address

23. 23 Example: ADD [200], [100]

24. 24 Disadvantages: One operand overwritten Still needs three memory accesses

25. 25 One-Address Format Only one location allowed for one operand and result, a location within the processor, called an accumulator historically. Other operand still in main memory, and its address given in instruction:

26. 26 Example ADD [100]

27. 27 Advantages: Shorter instruction Eliminates two memory accesses Faster accessing location inside processor than memory Disadvantages: Only one location for one operand and result Still needs one memory access

28. 28 Register Format Have more than one location within processor - set of registers. If there were 32 registers, say R0 to R31, 5 bits are required in each field to specify the register.

29. 29 Example ADD R1, [100]

30. 30 Register-Register Formats With registers, can now hold all operands in registers and operate on registers only: If 2 registers specified If 3 registers specified

31. 31 Example ADD R3,R1,R2

32. 32 Zero-Address Format Possible to eliminate all addresses by using specific locations. Then only the operation need be specified in the instruction Usually locations for operands/result are top two locations of a stack (a last-in first-out queue) in memory or implemented with registers within processor. Stack pointer - a register within processor used to hold the address of the top location.

33. 33 Example ADD Zero-address format useful to compilers for producing code for arithmetic expressions (using reverse Polish notation) Used by Burroughs in their computers in the 1960’s and not widely since (but re-introduced in SUN Java chip).

34. 34 We have outlined several instruction format possibilities: 3-address 2-address 1-address register formats (3 register or 2 register) zero-address A particular processor will not use all formats.

35. 35 Examples Intel 64/IA-32 instruction set processors (continuing early 8086 processor designs) From an external perspective, 2-address formats with one operand in a register, the other in a register or memory. IBM PowerPC, SUN Sparc processor and other so-called reduced instruction set computers 3-register format for arithmetic and register-memory format for accessing memory operands. More details later.

36. 36 Questions