45nm Processors & Beyond A Presentation On By Ajaypal Singh Dhillon Kurukshetra university

Contents Introduction Process Features Transistor Process flow 45nm Techniques Intel Penryn features Differences between AMD & INTEL technology Beyond 45nm Conclusions Refrences

Solution Use High-k material as gate dielectric Benefit compared to 65nm technology High-k Vs SiO 2 Benefits Capacitance60% greaterMuch faster transistor Gate dielectric leakage >10% reductionFar cooler

What’s so hard about using High-k Replacing SiO 2 with high-k materials leads to two problems due to interaction with the the polysilicon gate electrode: 1. Charges got traped at gate/dielectric interface Solution: Atomic layer Deposition 2. Phonon scattering- electrons are made less mobile (they slows down)

Solution: use metal gate

45nm techniques Immersion lithography Immersion effectively decreases wavelength by putting water between projection lens and silicon wafer If a fluid of refractive index n fills the space between the lens and the wafer, then the effective wavelength = the vacuum wavelength of the light ÷ by n Shorter effective wavelengths enable smaller features to be patterned Atomic layer Deposition

Intel Penryn features New Intel SSE4 Instructions Larger, Enhanced Intel Advanced Smart Cache High Speed Cores Fast Radix-16 Divider Nearly 400 million transistors in dual core and about 800 millions of transistors in 45nm quad core.

Difference between AMD & Intel Technology Amd uses immersion lithography where as Intel uses dry lithography at 45nm Amd uses Direct connect architecture for its processors where as Intel still happy to stick with FSB. Amd follows “Gate first” approach where as Intel follow “Gate Last”. Though Intel has not disclosed the metal it is using for gate where as it is believe that Amd is cashing on nickel in this prospective.

Beyond 45nm 32nm process after about three years from now. 16nm to arrive in 2018 with gate length 5nm. If gate length approaches 3nm, a chip that contained them would hypothetically overheat itself. 1.5nm is the minimum gate length a transistor can hit. Use carbon nanotubes, HP crossbar switches, vGroove, multiple gate transistors, 3D chips,Spintronics etc.

Conclusions A 45 nm technology is described with –Design rules supporting ~2X improvement in transistor density –193nm dry lithography at critical layers for low cost –8 standard Cu interconnect layers with extensive use of low-k –Thick Metal 9 Cu RDL with polymer ILD High-k + Metal gate transistors implemented for the first time in a high volume manufacturing process –Integrated with 3RDgeneration strained silicon –Achieve record drive currents at low IOFFand tight gate pitch The technology is already in high volume manufacturing –High yields demonstrated on SRAM and 3 microprocessors –High yields demonstrated in two 300mm fabs

Refrences 1. Article “The High-k Solution By Mark T. Bohr, Robert S. Chau, Tahir Ghani, and Kaizad Mistry” Published on October White Paper, Intel core micro architecture ”Introducing the 45nm next generation microarchitecture” October Technical intel paper”A 45 logic technology with high-k +metal gate transistors,strained silicon,9cu interconnect layers,193 dry pattering, 100% Pb free packing” Amd press reports

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