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Next Generation Integrated Circuits 300 mm wafers Copper metallization Low-K dielectric under interconnect lines High-K dielectric under gate Silicon-on-insulator.

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Presentation on theme: "Next Generation Integrated Circuits 300 mm wafers Copper metallization Low-K dielectric under interconnect lines High-K dielectric under gate Silicon-on-insulator."— Presentation transcript:

1 Next Generation Integrated Circuits 300 mm wafers Copper metallization Low-K dielectric under interconnect lines High-K dielectric under gate Silicon-on-insulator (SOI) Strained silicon New gate metals Dual-core CPU chips

2 Next Generation Integrated Circuits 300 mm wafers Copper metallization Low-K dielectric under interconnect lines High-K dielectric under gate Silicon-on-insulator (SOI) Strained silicon New gate metals Dual-core CPU chips

3 Copper Metallization – Low-K Dielectric

4 Next Generation Integrated Circuits 300 mm wafers Copper metallization Low-K dielectric under interconnect lines High-K dielectric under gate Silicon-on-insulator (SOI) Strained silicon New gate metals Dual-core CPU chips

5 High-K Gate Dielectric Reduced fringing of gate electric field – better switching control, less leakage current Reduced tunneling leakage current with thin oxides Si 3 N 4, ZrO 2, HfO 2

6 Next Generation Integrated Circuits 300 mm wafers Copper metallization Low-K dielectric under interconnect lines High-K dielectric under gate Silicon-on-insulator (SOI) Strained silicon New gate metals Dual-core CPU chips

7 Silicon-On-Insulator No p-n junction for electrical isolation Reduced inter-device coupling Reduced parasitic capacitance No deep diffusion required for isolation - less fabrication time, closer device packing

8 Next Generation Integrated Circuits 300 mm wafers Copper metallization Low-K dielectric under interconnect lines High-K dielectric under gate Silicon-on-insulator (SOI) Strained silicon New gate metals Dual-core CPU chips

9 Strained Silicon Enhanced carrier mobility – compensates for increased ionized impurity scattering in thin, heavily-doped layers

10 Next Generation Integrated Circuits 300 mm wafers Copper metallization Low-K dielectric under interconnect lines High-K dielectric under gate Silicon-on-insulator (SOI) Strained silicon New gate metals Dual-core CPU chips

11 New Generation ICs at Intel http://www.intel.com/technology/silicon/index.htm http://www.intel.com/technology/silicon/research.htm?iid=tech _sil+rd Main Page Reports and Publications

12 New Generation ICs at AMD http://www.thinkcp.com/AMD/roadmap.html Processor Cores Roadmap Main Page http://www.amd.com/us-en/

13 New Generation ICs at AMD Back to Main

14 New Generation ICs at IBM http://www.research.ibm.com/ http://www.ibm.com/search/?en=utf&v=11&lang=en&cc=&lv=w&q=%2 BNanofabrication%20%2Burl.all:research.ibm.com Main Page Reports and Publications http://www- 916.ibm.com/press/prnews.nsf/jan/0C17FDCBF4B76CE185256C6F0064206D Nanofabrication


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