GoetzPre-PDR Peer Review October 2013 FIELDS TDS FPGA Peer Review Keith Goetz University of Minnesota 1

GoetzPre-PDR Peer Review October 2013 TDS Time Domain Sampler TDS is a combination of analog electronics, digital electronics, VHDL firmware and flight software Added System-6 pieces fit in well –Low impact TDS FPGA is central RTAX4000 is the FPGA of choice RTAX4000SL-1 CCGA-1272 –Maybe more than we need in gates but has lots of pins CQ352 does not have enough user pins –FIELDS FPGA daughter board makes this a common part/design solution 2

GoetzPre-PDR Peer Review October 2013 TDS FPGA Block 3

GoetzPre-PDR Peer Review October 2013 TDS FPGA Block 4

GoetzPre-PDR Peer Review October 2013 TDS Data Acquisition/Control Gather time series data –Access ADCs –Front end processing Acquire SWEAP counts and sync Down sampling e-time series –Send buffered data stream to TDS memory controller Never skipping a beat Generate sampling clock Select muxes 5

GoetzPre-PDR Peer Review October 2013 TDS statistics Peaks and maxes Triggering Langmuir wave statistics Dust analysis High heritage 6

GoetzPre-PDR Peer Review October 2013 TDS Memory Control Accept data steam Accept triggers Control circular buffers –Large dedicated 32-bit memory path –Large dedicated event memory (16MB) Interleave memory access from CPU 7

GoetzPre-PDR Peer Review October 2013 TDS FFT Controller Optional Allows frequency analysis –Redundancy –Enhances dynamic range of new all-digital TNR Large signal spectra Could be done in hardware or software 8

GoetzPre-PDR Peer Review October 2013 HK ADC Controller New Allow FSW access to external ADC/MUX –Analog HK –Analog Science 9

GoetzPre-PDR Peer Review October 2013 S/C TM/TC Interface New UARTS to/from S/C –A/B –S/C Time, Status and Sharing –S/C commands –S/C telemetry HK MAGi –Provides one real-time clock –Common VHDL and FSW with DCB 10

GoetzPre-PDR Peer Review October 2013 Clocks Receive internal clock (from on-board oscillator) Receive external clock (from DCB) Fail-over and back –Slave to DCB when possible Generate clocks for internal/external use –MAGi CDI (4.8MHZ) and heater (300kHz) –SWEAP CDI (4.8MHz) and high-rate clock (19.2MHz) –AEB2 conversion clock (300kHz) –LNPS2 conversion clock (600kHz) –ADC clocking Maintain real-time clock from S/C Maintain real-time clock from DCB 11

GoetzPre-PDR Peer Review October 2013 Watchdog Handles resets Internal watchdog timer –Touched by FSW –If not touched delivers a reboot –Generally, the watchdog time is long 220s in the past 12

GoetzPre-PDR Peer Review October 2013 DCB CDI Standard CDI slave interface 4.8MHz Also includes high rate clock (38.4MHz) DCB sends TDS time and commands TDS sends DCB fully formed TDS CCSDS data packets –~10kbps Common VHDL and FSW with DCB 13

GoetzPre-PDR Peer Review October 2013 MAG CDI New Standard CDI master interface 4.8MHz Also includes power supply chopping frequency (300kHz) TDS sends MAG time and commands MAG sends TDS data chunks – one per cycle Common VHDL and FSW with DCB 14

GoetzPre-PDR Peer Review October 2013 SWEAP CDI New Standard CDI master interface –LVDS 4.8MHz Also includes high rate clock (19.2MHz) TDS sends SWEAP time and commands –CBS –MAG vector –Once per cycle SWEAP sends contributions to CBS 15

GoetzPre-PDR Peer Review October 2013 AEB Interface New Parallel and serial interface lines Controls Antenna Electronics Board parameters –Current and voltage biasing Retrieves AEB HK –Controlling AEB MUX Also includes power supply chopping frequency (300kHz) Common VHDL and FSW with DCB 16

GoetzPre-PDR Peer Review October 2013 LNPS Interface New Parallel interface lines Controls MAG power Retrieves LNPS HK –Controlling LNPS MUX Also includes power supply chopping frequency (600kHz) Common VHDL and FSW with DCB 17

GoetzPre-PDR Peer Review October 2013 Test UARTS Console –OOB commanding Log –OOB event stream GSE –OOB binary/packet data stream Debug Line drivers on GSE (mezz board) 18

GoetzPre-PDR Peer Review October 2013 Test points Board serial number Blinking light –Software controlled Test input ports Test output ports I/O to EM connector to allow timing/triggering tests 19

GoetzPre-PDR Peer Review October 2013 Processor LEON 3 IP –Free – open source –SPARC V8 –LEON 3 FT planned for flight –STEREO used an earlier version – SPARC V7 IP –Gaisler GRLIB LEON AHB/APB infrastructure GDB GRMON –UARTs 20

GoetzPre-PDR Peer Review October 2013 Processor Support Interrupts DMA Handler Processor RAM –Internal and external Processor ROM/PROM –Internal and external –Internal boot PROM? Processor EEPROM 21

GoetzPre-PDR Peer Review October 2013 Mezzanine Board GSE only RS-232 drivers Reset button Blinking light Logic Analyzer interfaces PROM/EPROM/EEPROM sockets –PROM emulator interface 22

GoetzPre-PDR Peer Review October 2013 TDS BB2 23

GoetzPre-PDR Peer Review October 2013 FPGA statistics 24