1. HinzeSPP/FIELDS iCDR – TDS FPGA 1 Solar Probe Plus / FIELDS Instrument CDR TDS FPGA Jason Hinze University of Minnesota jjh@bulldog-technolgies.com

2. HinzeSPP/FIELDS iCDR – TDS FPGA Introduction: TDS in Context – FIELDS Block Diagram 2

3. HinzeSPP/FIELDS iCDR – TDS FPGA TDS FPGA Block Diagram 3

4. HinzeSPP/FIELDS iCDR – TDS FPGA TDS FPGA Major Components LEON3FT SPARC V8 CPU (from GRLIB) AHB/APB bus logic (from GRLIB) General-Purpose Memory Controller (PROM, EEPROM, cpuSRAM) Spacecraft Interface (UART, with frame detection) DCB Interface (CDI Slave peripheral) MAGi Interface (CDI Master peripheral) SWEAP Interface (CDI Master peripheral) Real-Time Clocks and Timestamping TDS Data Acquisition & Control TDS Event Memory Controller High-Speed Clock Management (detection, sync, failover) Analog Housekeeping (TDS local, LNPS2, AEB2) 4

5. HinzeSPP/FIELDS iCDR – TDS FPGA Spacecraft Interface 115.2kbaud UART TX FIFO –512 x 13 bit (8 bits data + 5 bits EDAC/SECDED) –Generates low-water interrupt RX FIFO –512 x 13 bit (8 bits data + 5 bits EDAC/SECDED) –Generates high-water interrupt Start-of-Cycle Virtual PPS (“V1PPS”) Detector –Detects falling edge on RX after inactivity (>100ms) –Generates interrupt –Provides pulse for use by other peripherals EOF Detector –Detects periods of inactivity on RX (>100ms) –Generates interrupt 5

6. HinzeSPP/FIELDS iCDR – TDS FPGA DCB Interface (CDI Slave Peripheral) 4.8MHz Synchronous Serial Interface TX FIFO –256 x 22 bit (16-bit CDI telemetry values + 6 bits EDAC/SECDED) –Generates low-water interrupt RX FIFO –256 x 32 bit (24-bit CDI command + parity & framing error indicators + 6 bits EDAC/SECDED) –Generates high-water interrupt Real-Time Clock Synchronization Support – DCB to TDS –FIELDS Start-of-Cycle Detector Detects FIELDS Start-of-Cycle CDI command (“F0”) Provides Sample Cycle sync value to Real-Time Clock peripheral (RTCS) Provides pulse for use by other peripherals Generates interrupt for software use –MET Sync Value Capture Captures MET sync value (“the time at the tone will be...”) Provides MET sync value to Real-Time Clock peripheral (RTCS) 6

7. HinzeSPP/FIELDS iCDR – TDS FPGA MAG/SWEAP Interface (CDI Master Peripheral) 4.8MHz Synchronous Serial Interface TX FIFO –128 x 30bit (24-bit CDI commands + 6 bits EDAC/SECDED) –Generates low-water interrupt –Hardware-triggered TX start at specified subcycle count (x4) RX FIFO –256 x 22bit (16-bit CDI telemetry values + 6 bits EDAC/SECDED) –Generates high-water interrupt RX inactivity (EOF) Detector –Generates interrupt after RX inactive for programmable number of cycles Subcycle Sync Support –Four sync pulses from RTCS (at specified subcycle counts) –Can be used to start TX –Can generate interrupts 7

8. HinzeSPP/FIELDS iCDR – TDS FPGA RTCS Real-Time Clocks sMET – MET derived from spacecraft interface –sMET sync value provided by software after parsing Spacecraft Time and Status Message –sMET is synced at next spacecraft start-of-cycle (“V1PPS”) dMET – MET derived from DCB interface –dMET sync value provided by hardware-captured MET sync commands –dMET is synced at FIELDS start-of-cycle (“F0”) FSCT – FIELDS Sample Clock Time (cycles:subcycles) –FSCT sync value provided by hardware-captured start-of-cycle command –FSCT is synced at FIELDS start-of-cycle (“F0”) SYST – System Time (# bus clocks since reset) TSCT – TDS Sample Clock Time (# sample vectors since reset) 8

9. HinzeSPP/FIELDS iCDR – TDS FPGA RTCS Hardware Timestamping Hardware timestamps capture all RTC values in a single cycle Hardware timestamps can be triggered by a variety of sources: –Spacecraft start-of-cycle (“V1PPS” from spacecraft) –FIELDS start-of-cycle (“F0” from DCB) –TDS Event Done pulse –SWEAP Start pulse –Software-driven Triggers (3) Each trigger source has its own set of timestamp capture registers This gives us precise and detailed capability to derive science data timestamps and to track all of the various timebases in our system. 9

10. HinzeSPP/FIELDS iCDR – TDS FPGA TDS Instrument TDS samples five analog channels and SWEAP counts at 1.92M sample vectors per second –Samples are 16 bit signed integers. Events are triggered when a peak is at the desired peak location. (usually the center) –When an event is triggered, a hardware timestamp is taken and an interrupt is generated, and the “next event” metadata are moved to the “current event” metadata registers. –Software sets up the “next event” metadata while the current event is being acquired. TDS Event Memory: 16MB on a dedicated external bus (4M x 32-bit) –Dual-ported: acquisition hardware & AHB –Acquired samples are written in first half of AHB clock cycle –AHB transactions are serviced in second half of AHB clock cycle. 10

11. HinzeSPP/FIELDS iCDR – TDS FPGA Synchronized High-Speed Clock Selection The TDS must use high-speed clock provided by the DCB, if it is available. This is done to synchronize data acquisition and noise due to power supply harmonics. So, the TDS must detect presence and sanity of the DCB high- speed clock. –Compare counters driven by local high-speed clock and DCB high- speed clock to determine if DCB high-speed clock is present and well- behaved. Also, the TDS must gracefully switch to the DCB high-speed clock after booting. (if the DCB high-speed clock appears to be good) –Standard synchronized clock-switching circuit used. Clock Control peripheral allows software to monitor state of DCB HSCLK and select which clock to use as the system master clock. 11

12. HinzeSPP/FIELDS iCDR – TDS FPGA Current RTAX4000S FPGA Resource Use 12 ResourceUsedAvailablePercent Used R-cell6,95520,16034% C-cell13,91040,32034% RAM Block10012083% I/O (D’board)273~350~78% I/O (FPGA)27384032%

13. HinzeSPP/FIELDS iCDR – TDS FPGA Final RTAX4000S FPGA Resource Use (Estimated) 13 ResourceUsedAvailablePercent Used R-cell13,45020,16067% C-cell26,90040,32067% RAM Block8412070% I/O (D’board)236~350~67% I/O (FPGA)24984030%

14. HinzeSPP/FIELDS iCDR – TDS FPGA Parts and Materials We use the interchangeable FIELDS FPGA daughterboard system developed by our friends at UCB. 14 We will migrate to the use of the RTAX4000SL-1CG1272 version of the daughterboard as development proceeds. Current development takes place on the A3PE3000- FG484 version of the FIELDS FPGA daughterboard. (shown to the right, in its home on TDS EM1)

15. HinzeSPP/FIELDS iCDR – TDS FPGA Pre-iCDR Peer Review TDS FPGA Peer Review held 2014 Dec 5 Peer review resulted in 7 recommendations. All will be implemented in the near term. 15

16. HinzeSPP/FIELDS iCDR – TDS FPGA Ongoing Development AEB interface peripheral (DAC interface, DIOs; based on DCB VHDL) LNPS interface peripheral (DIOs) MAG CDI Clock & Command signal gating (MAG FPGA cooldown) Count SWEAP pulses Generate additional TDS data products (moments, maxes) Migrate from LEON3 to LEON3FT EDAC on FPGA RAM used for FIFOs 16

17. HinzeSPP/FIELDS iCDR – TDS FPGA Conclusion We have no outstanding issues. TDS FPGA currently successfully performs most major functions 24x7. TDS FPGA is ready to continue into FM development. 17

18. HinzeSPP/FIELDS iCDR – TDS FPGA Backup Slides 18

19. HinzeSPP/FIELDS iCDR – TDS FPGA Peer Review Recommendations 19 ActionNameDescriptionResponseClosed? FPGA-01EDAC Determine what internal FPGA memories need EDAC or other protection. Consider failure modes and expected SEU rates. Even a parity bit (which is sometimes free) and associated error flag might be better than nothing. We will use EDAC or TMR for all custom-IP uses of FPGA SRAM. Long-duration state storage (if any) will be scrubbed, ephemeral storage (active FIFOs / buffers) will not. Note that the LEON3FT uses FPGA SRAM for cache; cache lines are parity protected and automatically flushed on parity error. y FPGA-02ADC read noise Verify (by test) that ADC read does not impact conversion. Might imagine that the value of the data being read impacts the subsequent conversion. We will perform this test in the near term, after the EM TDS analog section has been tuned and characterized. y FPGA-03DCB Clock Quality Consider tighter requirements on DCB clock quality in clock selection logic - might get messy DCB clock as it is powered down. We will implement a tightly bracketed algorithm for DCB clock detection. y FPGA-04Housekeeping cycle AEB noiseConsider changing housekeeping collect cycle to minimize noise into AEB. We will change the analog housekeeping collection system to operate the AEB analog housekeeping multiplexer only when needed. y FPGA-05Dust Events Need a requirement on system to reject dust events (hardware and/or software). We have a proven dust detection algorithm that we will implement. Addition of a formal requirement for this is pending. y FPGA-06FPGA Simulation Top level FPGA simulation are strongly recommended. Modeling the board (memories, etc) allows for running processor from a testbench based "BootROM". Having this check in place reduces a lot of risk, particularly when migrating from the ProASIC to the RTAX. We will implement a VHDL test rig and perform full FPGA simulations before burning our flight RTAX. y FPGA-07LEON Fault Tolerant version Migrate to the "Fault Tolerant" version of the LEON Processor as soon as is feasible. FPGA resources and system behavior might be impacted, and it would be good to know sooner rather than later. We have obtained the LEON3FT IP from the vendor and will migrate shortly after iCDR. y