Domino Ring Sampler (DRS) Readout Shift Register Speed Control (V) 2 – 4 GHz Inverter Domino Chain Rotating sampling wave Synchr Domino Wave Domino Wave 1024 cells Impulse Analog input The new Data Acquisition System is based on the Domino Ring Sampler chip, a schematic view of the device is shown in figure: We have three main parts: the ring of inverters, that is composed of 1024 cells, the array of capacitors that store the samples of the analog signal, there are 12 arrays, where each cell can be read addressing the array and using a shift register @ 40 MHz. The working principles is the following: an impulse is injected in the ring, this impulse is called Domino Wave, and it progates into the ring enabling one by one the cells of the arrays. In this way the Capacitor that is enabled can sample the analog signal. When a trigger occurs the Domino Wave is stopped immediately and using the shift register the samples are read @ 40 MHz. Currently we are using the DRS version 2 but we are waiting the new version, the DRS version 4 that has the following innovative characteristics: Analog output Clock 40MHz SROUT Readout Shift Register SRIN SRCLK SRCLK SRRES

Differential Amplifier RECEIVER BOARD CONNECTOR DRS2 Mezzanine PULSAR CONNECTOR SINGLE ENDED DIFFERENTIAL DRS2 Input Stage High BW Differential Amplifier TRIGGER SERIAL P.I. ADC/DAC PLL CLK POWER SUPPLY We have developed a dedicated board, called DRS2 Mezzanine, that houses two DRS chips. The input signal stage for signal conditioning, the temperature sensor and voltage monitor are placed on the mezzanine as well. Two AD9235 ADCs convert the analog signal on 12 bit, each for one Domino. Two PLLs are housed on the Mezzanine, in the bottom side, to synchronize the Domino Wave in each chip with the external reference clock bring up to the mezzanine. The VHDL firmware control all the hardware placed on the DRS2 mezzanine, at this point I would like to introduce the: T SENSOR 40 MHz ADC (AD9235 12 – bit) RECEIVER BOARD CONNECTOR 2 PLLs (in BOTTOM side)

TRIGGER DISTRIBUTION BOARD M E Z Z S V T I N S V T O U T L 1 I N L 1 O U T BUSY PULSAR D I G I TAL ANALOG CPUVME 1 5 6 VME CRATE 1 12 7 VME CRATE 2 TRIGGER DISTRIBUTION BOARD CLOCK DISTRIBUTION BOARD RECEIVER BOARDS: 1039 CAMERA SIGNALS 10 11 25 26 52 51 From TRIGGER SYSTEM 24 2 ABORTBUSY DIGITAL DATA ABORT

ANALOG PULSAR DRS ADC S-Link fiber PC VME Backplane 1 3 2 DATAIO2 DATAIO1 CTRL VME S-LINK HOLA BUSY VME Backplane Pulsar Board (VME 9U) Auxiliary Board SRAM DRS ADC TRIGGER Analog Data Trigger Cell…. S V T Trigger Cell….. SVT IN SVT OUT TRIGGER, BUSY… Data PLL Clock S-Link F I L A R fiber PC This is the ANALOG PULSAR frame. In normal circumstances the Domino chips are in samplig state. When a trigger occurs the VHDL code, loaded in each FPGA, that I usually call Sequencer, stops the Domino Wave, and the board goes in a IDLE state, where it waits that the trigger cell arrives. When it happens, the Sequencer detect the region of interest and the readout phase starts. So the Data into the Domino chips are read, formatted and only the data cell in the ROI are stored in the external SRAM. This task is executed in parallel by the DATAIO1 and 2 FPGAs that control 2 DRS2 Mezzanine each. When an entire event has been acquired, if there are not event to be readout, the Data into the SRAMs are read and sent to the CONTROL FPGA. This FPGA handles the data and sends them, through the P3 connector, to the HOLA board. HOLA transmits the data to the FILAR board that stores them into the mass storage system. In parallel the CONTROL FPGA has to be propagate the trigger cell to the next ANALOG PULSAR.

Trigger Cell and Trigger Number DIGITAL PULSAR DATAIO1 P 1 3 2 CTRL VME BUSY Board TRIGGER, BUSY… DIGITAL MODULE Trigger Number VME Backplane Pulsar Board (VME 9U) Auxiliary Board SRAM DRS ADC TRIGGER signal SVT OUT to the first ANALOG PULSAR S V T SVT IN from the last L Trigger Cell and Trigger Number PLL Clock Busy Trigger number 32 23 This is the DIGITAL PULSAR frame. When a trigger occurs, the sampling phase is stopped. The VHDL code loaded in the DATAIO1 FPGA, detect the trigger cell and sends it to the CONTROL FPGA that trasmits this information and other data, to the first ANALOG PULSAR via SVT cable. In parallel the readout data from the Domino are stored in the external SRAM.

ANALOG DATAIO FPGA ADCx2 ADCx2 VME INTERFACE DATA BLOCK DATA BLOCK RAM 2 DRS2 cards ANALOG DATAIO FPGA DATA DATA Send ADCx2 ADCx2 VME INTERFACE DATA BLOCK DATA BLOCK 24 CLK40MHz Sstart CLK40MHz CLK40MHz DATA DATA DATA RAM RAM 32 VME SIGNALS ADCx2 ADCx2 24 HOLD SE_WORD CH_WORD EE_WORD SVT IN SVT IN CABLE TRIG CELL-TRIG NUMB TRIGGER Send Sstart VME SIGNALS DATAEN SRAM CONTROLLER CLK40MHz SUPER SEQUENCER SUPER SEQUENCER CLK40MHz DATA WREN CEN ADDR UDATA UWE LFF BUSY 17 32 A Schematic view of the Sequencer is shown in the figure. Under normal circumstances the Domino chips are in sampling state. The Sequencer sets up the samplers using the START_DOMINO signal. This signal activates the DRS CONTROL block that generates a 6 ns wide pulse that is injected in the Inverter Domino Chains of the 4 Domino chips, the Domino Wave. The Domino chips sample the analog signal continuously, storing the data in the ring buffers. When a trigger signal occurs, the Sequencer stops the Domino wave, sets up the ADCs for the analog to digital conversion and the internal DRS shift registers for reading the data, then waits for the trigger cell from the DIGITAL PULSAR or from the previous ANALOG PULSAR. Once the trigger cell arrives, the Sequencer detect the ROI and begins the readout phase. The analog data are converted by two ADCs at high resolution (12 bits) at 40 MHz and sent to the DATAIO. The DATA from one mezzanine are read and stored in the EX-SRAM on-line, while the Data of the other mezzanine are temporarily stored in an RAM inside the FPGA and after stored into the EX-SRAM. The reason of this is that the SRAM data bus is 32 bits deep while the Data word is 64 bits deep. Only the data inside the ROI are stored into the SRAM in order to reduce the DATA FLOW. When the Sequencer block is not busy reading from the Domino chips, the CONTROL FPGA retrieves the stored data and sends them to the transmission board through the VME P3 connector and then to the FILAR boards via S-Link housed in a PC where the data are stored. ST_RD ST_DRS SRCKEN ADCCKEN CH_ADD 32 4 CONTROL FPGA CONTROL FPGA SRAM SRAM CTRL SIGNALS CLK40MHz HOLA HOLA HOLA UDATA UDATA UWE UWE LFF LFF Mezzanines Hardware Mezzanines Hardware DRS CONTROL DRS CONTROL 32 32 SRRES SRCLK P3 P3 FILAR FILAR FILAR SRIN PC PC

PULSer And Recorder DIGITAL PULSAR ANALOG PULSAR DRS Mezzanine Trigger Number, Digital Data Trigger Cell ANALOG PULSAR Read-Out System, Data Format Trigger Cell and Trigger Number propagation via SVT cable Region-of-Interest: 100 samples DRS Mezzanine fc = 2.5 GHz 1 Domino cell = 0.4 ns RoI Read-out system of 1200 channels: 1 Digital + 15 Analog PULSARs 1024 samples/ch ~2,4 GBytes/s @ 1 kHz max 4 h Acquisition Time ~34 TBytes With Region of Interest (RoI): 100 samples/ch 240 MBytes/s @ 1 kHz max 4 h Acquisition Time ~3,4 TBytes Trigger Latency I have told that the software calculates the latency of the trigger signal. Actually the code in the PULSAR board executes this task and use this information to calculate the ROI of each event. We use a PULSAR in two way: DIGITAL PULSAR and ANALOG PULSAR. So, on the DIGITAL PULSAR one DRS2 Mezzanine is plugged with a single DRS2 chip on board. This DRS2 samples the trigger signal. The DIGITAL PULSAR role is to find the cell, inside the ring buffer, where the rise edge of the trigger occurs, called trigger cell. In this way we can detect the start point of the event, that has to be acquire, inside the ring buffer, using the trigger latency. In this way we can reconstruct the Region Of Interest (ROI) where the information has been sampled. We have to do it because a system formed by 15 PULSARs, with a 1024 samples/CH, gives a Data Flow of about 2,4GBytes/s @ 1kHz of trigger rate. Instead if only a small region of the ring buffer is selected the Data Flow is reduced, for example of an order of magnitude if a 100samples/ch is taken. The readout phase is executed by the ANALOG PULSAR that has to select the region of interest, readout the sampled data into the Domino and propagates the trigger cell to the others ANALOG PULSARs. 250 cells wide 100 cells wide

Data Acquisition System Daisy- chained distribution of trigger number and trigger cell The figure reports a schematic view of the entire system. The system is composed of 15 ANALOG PULSAR boards and one DIGITAL pulsar. When the trigger occurs the sampling phase is stopped in all DRS chips. The DIGITAL PULSAR detects the trigger cell and sends it to the first ANALOG PULSAR. This boards progates this information to the next and begins the readout phase. Consistence Tests and verify

Trigger Cell Trigger Number DIGITAL PULSAR DATAIO1 P 1 3 2 CTRL VME BUSY Board TRIGGER, BUSY… DIGITAL MODULE IPR SCALER VME Backplane Pulsar Board (VME 9U) Auxiliary Board SRAM DRS ADC TRIGGER SVT OUT S V T SVT IN L Trigger Cell Trigger Number PLL Clock This is the DIGITAL PULSAR frame. When a trigger occurs, the sampling phase is stopped. The VHDL code loaded in the DATAIO1 FPGA, detect the trigger cell and sends it to the CONTROL FPGA that trasmits this information and other data, to the first ANALOG PULSAR via SVT cable. In parallel the readout data from the Domino are stored in the external SRAM.

ANALOG PULSAR DRS ADC DRS ADC DRS ADC S-Link DRS ADC Pulsar Board (VME 9U) VME Backplane P 1 DRS ADC SVT IN VME PLL Clock F I L A R DATAIO1 Analog Data DRS ADC P P 2 TRIGGER SRAM CTRL DRS ADC SVT IN Trigger Cell….. S V T S-Link This is the ANALOG PULSAR frame. In normal circumstances the Domino chips are in samplig state. When a trigger occurs the VHDL code, loaded in each FPGA, that I usually call Sequencer, stops the Domino Wave, and the board goes in a IDLE state, where it waits that the trigger cell arrives. When it happens, the Sequencer detect the region of interest and the readout phase starts. So the Data into the Domino chips are read, formatted and only the data cell in the ROI are stored in the external SRAM. This task is executed in parallel by the DATAIO1 and 2 FPGAs that control 2 DRS2 Mezzanine each. When an entire event has been acquired, if there are not event to be readout, the Data into the SRAMs are read and sent to the CONTROL FPGA. This FPGA handles the data and sends them, through the P3 connector, to the HOLA board. HOLA transmits the data to the FILAR board that stores them into the mass storage system. In parallel the CONTROL FPGA has to be propagate the trigger cell to the next ANALOG PULSAR. DATAIO2 Trigger Cell…. SVT IN P 3 S V T DRS ADC TRIGGER, BUSY… S-LINK HOLA BUSY SVT OUT Data SRAM Auxiliary Board

DATA BLOCK SUPER SEQUENCER SRAM CONTROLLER VME INTERFACE DRS CONTROL SE_WORD CH_WORD EE_WORD TRIGGER READING ST_DRS ST_RD CH_ADD 32 24 SRCKEN DATAEN ADCCKEN VME INTERFACE WREN ADDR CEN 17 DRS CONTROL CTRL SIGNALS 4 FPGA DATAIO FPGA LFF UWE UDATA VME SIGNALS SIGNALS P3 HOLA ADCx2 2 DRS Cards Mezzanines Hardware FILAR PC CLK40MHz SRRES SRCLK SRIN RAM A Schematic view of the Sequencer is shown in the figure. Under normal circumstances the Domino chips are in sampling state. The Sequencer sets up the samplers using the START_DOMINO signal. This signal activates the DRS CONTROL block that generates a 6 ns wide pulse that is injected in the Inverter Domino Chains of the 4 Domino chips, the Domino Wave. The Domino chips sample the analog signal continuously, storing the data in the ring buffers. When a trigger signal occurs, the Sequencer stops the Domino wave, sets up the ADCs for the analog to digital conversion and the internal DRS shift registers for reading the data, then waits for the trigger cell from the DIGITAL PULSAR or from the previous ANALOG PULSAR. Once the trigger cell arrives, the Sequencer detect the ROI and begins the readout phase. The analog data are converted by two ADCs at high resolution (12 bits) at 40 MHz and sent to the DATAIO. The DATA from one mezzanine are read and stored in the EX-SRAM on-line, while the Data of the other mezzanine are temporarily stored in an RAM inside the FPGA and after stored into the EX-SRAM. The reason of this is that the SRAM data bus is 32 bits deep while the Data word is 64 bits deep. Only the data inside the ROI are stored into the SRAM in order to reduce the DATA FLOW. When the Sequencer block is not busy reading from the Domino chips, the CONTROL FPGA retrieves the stored data and sends them to the transmission board through the VME P3 connector and then to the FILAR boards via S-Link housed in a PC where the data are stored.

DATA FORMAT

Data Acquisition System Daisy- chained distribution of trigger number and trigger cell The figure reports a schematic view of the entire system. The system is composed of 15 ANALOG PULSAR boards and one DIGITAL pulsar. When the trigger occurs the sampling phase is stopped in all DRS chips. The DIGITAL PULSAR detects the trigger cell and sends it to the first ANALOG PULSAR. This boards progates this information to the next and begins the readout phase. Consistence Tests