1 Stephen Jang Kevin Chung Xilinx Inc. Alan Mishchenko Robert Brayton UC Berkeley Power Optimization Toolbox for Logic Synthesis and Mapping

2 Outline  Introduction  Background  Contributions SimSwitch: Switching activity estimation SimSwitch: Switching activity estimation PowerMap: Mapping for power reduction PowerMap: Mapping for power reduction PowerDC: Re-synthesis for power reduction PowerDC: Re-synthesis for power reduction  Experiments  Conclusions

3 Introduction  High power dissipation is a rising concern  It was shown that, in FPGAs, 2/3 of dissipation is due to dynamic power [J. Anderson, F. N. Najm, FPGA’02]  Minimization of dynamic power is achieved by reducing the total switching activity of the nodes  This work Uses sequential simulation to estimate switching Uses sequential simulation to estimate switching Controls switching during synthesis and mapping Controls switching during synthesis and mapping f is the clock frequency, V the supply voltage, C i the capacitance switched by signal i, and S i is the probability of signal i making a transition (switching)

4 Background  Boolean network And-Inverter Graphs And-Inverter Graphs  Technology mapping LUTs and standard cells LUTs and standard cells  SAT-based re-synthesis Resubstitution with don’t-cares Resubstitution with don’t-cares

5 AIGs: Unifying Representation  An underlying data structure for various computations Rewriting, resubstitution, simulation, SAT sweeping, induction, etc are based on the same AIG manager Rewriting, resubstitution, simulation, SAT sweeping, induction, etc are based on the same AIG manager  A unifying representation for the whole synthesis/mapping/resynthesis/verification flow Synthesis, mapping, verification use the same data-structure Synthesis, mapping, verification use the same data-structure Allows multiple structures to be stored and used for mapping Allows multiple structures to be stored and used for mapping  The main functional representation in ABC A foundation of “contemporary logic synthesis” A foundation of “contemporary logic synthesis”

6 AIG Definition and Examples cd ab F(a,b,c,d) = ab + d(ac’+bc) F(a,b,c,d) = ac’(b’d’)’ + c(a’d’)’ = ac’(b+d) + bc(a+d) cd a b nodes 4 levels 7 nodes 3 levels bcac a b d acbdbcad AIG is a Boolean network composed of two-input ANDs and inverters

7 Three Tricks That Make AIGs Tick  Structural hashing Makes sure AIG is always stored in a compact form Makes sure AIG is always stored in a compact form Is applied during AIG construction Is applied during AIG construction Propagates constantsPropagates constants Ensures each node is structurally uniqueEnsures each node is structurally unique  Complemented edges Represents inverters as attributes on the edges Represents inverters as attributes on the edges Leads to fast, uniform manipulationLeads to fast, uniform manipulation Does not use memory for invertersDoes not use memory for inverters Leads to efficient structural hashingLeads to efficient structural hashing  Memory allocation Uses fixed amount of memory for each node Uses fixed amount of memory for each node Can be done by a simple custom memory managerCan be done by a simple custom memory manager Even dynamic fanout manipulation is supported!Even dynamic fanout manipulation is supported! Allocates memory for nodes in a topological order Allocates memory for nodes in a topological order Optimized for traversal in the same topological orderOptimized for traversal in the same topological order Small static memory footprint for many applicationsSmall static memory footprint for many applications ab c d ab c d Without hashing With hashing

8 SimSwitch  Fast sequential logic simulator Useful for switching activity estimation Useful for switching activity estimation  Improvements in simulation Compact logic representation Compact logic representation only 12 bytes per AIG nodeonly 12 bytes per AIG node Recycling simulation memory Recycling simulation memory allocate simulation memory only for nodes on the frontierallocate simulation memory only for nodes on the frontier Bit-parallel simulation of two time frames Bit-parallel simulation of two time frames When comparing simulation info in two consecutive time frames, avoids storing the simulation info from the previous frameWhen comparing simulation info in two consecutive time frames, avoids storing the simulation info from the previous frame

9 Simulation Runtime Evaluation Intel Xeon 2-CPU 4-core computer with 8GB RAM. Less than 100Mb was used in these experiments.

10 Review of Cut-Based Mapping Input: And-Inverter Graph 1. Compute K-feasible cuts for each node 2. Compute best arrival time at each node In topological order (from PI to PO) In topological order (from PI to PO) Compute the depth of all cuts and choose the best one Compute the depth of all cuts and choose the best one 3. Iterate area recovery Using area flow Using area flow Using exact local area Using exact local area 4. Chose the best cover In reverse topological order (from PO to PI) In reverse topological order (from PO to PI) Output: Mapped netlist S. Chatterjee et al, “Reducing structural bias in technology mapping”, Proc. ICCAD’05.

11 Cost Functions  Area flow  Wire flow  Switching flow (J. Cong, FPGA’99 S. Chatterjee, ICCAD’05) (S. Jang, FPGA’08) (This work)

12 Understanding a Cost-Function Flow

13 SAT-based Re-synthesis Framework  SAT-based re-synthesis (FGPA’09) has these features substantial optimization power substantial optimization power due to the use of internal don’t-caresdue to the use of internal don’t-cares scalable local computation scalable local computation due to the use of windowingdue to the use of windowing practical computation speed practical computation speed due to the use of Boolean satisfiability for functional manipulationdue to the use of Boolean satisfiability for functional manipulation ability to use various optimization objectives ability to use various optimization objectives due to the flexible conceptual framework.due to the flexible conceptual framework.

14 Two Ways to Cool Down a Hot Wire

15 Experimental Setup  Considered 20 industrial designs (12K to 165K 6-LUTs)  Used Intel Xeon 2-CPU 4-core computer with 8GB RAM  Verified the results using command “cec” in ABC  Experimental runs performed: Baseline: comb synthesis with choices Baseline: comb synthesis with choices (dch; if –e) 2 (WireMap [FGPA’08] is disabled)(dch; if –e) 2 (WireMap [FGPA’08] is disabled) FullOpt: complete flow including high-effort seq and synthesis FullOpt: complete flow including high-effort seq and synthesis (scl; lcorr; scorr) + (dch; if) 2 (WireMap is enabled)(scl; lcorr; scorr) + (dch; if) 2 (WireMap is enabled) PowerMap: power-aware LUT-mapping PowerMap: power-aware LUT-mapping FullOpt + (dch; if –p) 2FullOpt + (dch; if –p) 2 PowerDC: power-aware resynthesis PowerDC: power-aware resynthesis PowerMap + (mfs –p) 2PowerMap + (mfs –p) 2

16 Experimental Data

17 Power Reduction due to Power-Aware Optimization Table 1: Inputs toggle rate is 0.25 Table 2: Inputs toggle rate is 0.50 The results are geometric averages over 20 industrial designs

18 Changes in Wire Ratios due to Power-Aware Optimization Wire group codes: T5: “hot wires” (p > 0.4) … T1: “cold wires” (p 0.4) … T1: “cold wires” (p < 0.1) where p is the probability of switching (note that p can be more than 0.5)

19 Power Dissipation per Wire Group With / Without Power-Aware Optimization Wire (Wire2) are wires before (after) synthesis. Pwr (Pwr2) are power dissipations before (after) synthesis.

20 Conclusions  Presented several contributions SimSwitch: Estimation of switching activity SimSwitch: Estimation of switching activity PowerMap: An extension of the priority cut LUT mapper [ICCAD’07] to prioritize cuts based on switching activity of the nodes PowerMap: An extension of the priority cut LUT mapper [ICCAD’07] to prioritize cuts based on switching activity of the nodes PowerDC: An extension of SAT-based resynthesis [FPGA’09] to remove signals with high switching PowerDC: An extension of SAT-based resynthesis [FPGA’09] to remove signals with high switching  Demonstrated reductions in switching activity (without degradation of area and delay) 27% reduction due to seq synthesis [ICCAD’08] and WireMap [FPGA’08] against a plain-vanilla flow 27% reduction due to seq synthesis [ICCAD’08] and WireMap [FPGA’08] against a plain-vanilla flow +19% reduction due to PowerMap and WireDC described in this paper +19% reduction due to PowerMap and WireDC described in this paper

21 Future Work  Speeding up switching activity estimation Current implementation can be made faster Current implementation can be made faster  More accurate power estimation Estimating glitching in addition to switching Estimating glitching in addition to switching  Making other transforms power-aware Computing power-aware choices Computing power-aware choices Specialized logic structuring (power gating) Specialized logic structuring (power gating)  Sequential techniques for power reduction Clock-gating that uses induction to compute signals that are valid clock gates on the reachable states Clock-gating that uses induction to compute signals that are valid clock gates on the reachable states