1. Logic Synthesis: Past, Present, and Future
Alan Mishchenko
UC Berkeley

2. Overview Introduction Traditional logic synthesis
Modern logic synthesis
Formal verification
Conclusions

3. Introduction Design sizes increase
Larger logic circuits have to be handled
in both design and verification
Large Boolean expressions arise in other applications
cryptography, risk analysis, computer-network verification, etc
Development of logic synthesis methods continues
New methods are being discovered (in particular, SAT-based)
Scalability of the traditional methods is improved
Scalability is a “moving target”

4. Logic Synthesis: Definition
Given a function, derive (synthesize) a circuit
Given a poor circuit, improve it
Truth table: 0x
Circuit:
K-map:
Sum of products:
d e f \ a b c
000 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 |
001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
011 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
010 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 |
110 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 |
111 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
100 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 |
.i 6
.o 1

5. Other Representations of Boolean Functions
Truth table (TT)
Sum-of-products (SOP)
Product-of-sums (POS)
Binary decision diagram (BDD)
And-inverter graph (AIG)
Logic network (LN)
abcd F
0000
0001
0010
0011 1
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111 a b c d F 1 a b c d F a b c d F ab
x+cd
F = ab+cd
F = (a+c)(a+d)(b+c)(b+d)

6. What Representation to Use?
For small functions (up to 16 inputs)
TT works the best (local transforms, decomposition, factoring, etc)
For medium-sized functions ( inputs)
In some cases, BDDs are still used (reachability analysis)
Typically, it is better to represent as AIGs
Translate AIG into CNF and use SAT solver for logic manipulation
Interpolate or enumerate SAT assignments
For large industrial circuits (>100 inputs, >10,000 gates)
Traditional LN representation is not efficient
AIGs work remarkably well
Lead to efficient synthesis
Are a natural representation for technology mapping
Easy to translate into CNF for SAT solving
etc

7. Historical Perspective
Problem Size
ABC
100000
SIS, VIS, MVSIS
100
Espresso, MIS, SIS 50
AIG 16
CNF
BDD
SOP TT
1980
1990
2000
2010
Time

8. Traditional Logic Synthesis
SOP minimization
Logic network representation
Algebraic factoring
fast_extract algorithm
Don’t-care-based optimization

9. SOP Minimization SOP = Sum-of-Products (e.g. F = ab + cd + abc)
Given an SOP, minimize the number of products
Exact and heuristic minimization
SOP minimization is important because traditional logic synthesis uses SOPs for factoring and node minimization
Tools:
MINI (IBM, 1974), by S. J. Hong, R. G. Cain, D. L. Ostapko.
Espresso-MV (IBM / UC Berkeley, 1986) by R. Brayton, R. Rudell

10. Logic Network Representation
In traditional logic synthesis, netlists are represented as DAGs whose nodes can have arbitrary logic functions
Similar to standard-cell library, with any library gates
This representation is very general but it is not well-suited for implementing fast/scalable transformations
Later we will introduce a better representation

11. Algebraic Factoring SOP is a two-level (AND-OR) circuit
In most applications, a multi-level circuit is needed
Algebraic factoring derives a multi-level circuit from a (minimized) SOP
Factoring of integers and polynomials is similar
48 = 2 * 2 * 2 * 3
a2 - b2 = (a + b)*(a - b)

12. fast-extract Algorithm
fast-extract (J. Vasudevamurthy and J. Rajski, ICCAD’90) is often used for algebraic factoring in practice
It takes a set of SOPs and considers all two-cube divisors and single-cube two-literal divisors
It uses the priority queue to decide what divisor to extract
It updated the SOP and the priority queue after extracting each divisor
The resulting factored form is then further synthesized by other methods

13. Traditional Don’t-Care-Based Optimization
It is a complicated Boolean problem with many variations and improvements – hard to select one “classic algorithm”
Below we consider the work of H. Savoj and R. Brayton in early 1990’s
Compute compatible subsets of observabilty don’t-cares (CODCs) for all nodes in one sweep
For each node in some order, project don’t-cares into a local space, and minimize the node’s representation
Don’t-care are represented using BDDs, the node using SOPs
The resulting network has smaller local functions
The results of mapping in terms of area and delay are often improved
Implementation in SIS (full_simplify) has not been widely used
Slow and unscalable in many cases

14. Recent Developments Overview New representations Synthesis Mapping
Verification

15. Overview of Recent Developments
Using AIGs to represent circuits in all computations
Using simulation and SAT for Boolean manipulation
Achieving (near-) linear complexity in most algorithms by performing iterative local computations
Often using pre-computed data, hashing, truth tables, etc
Scaling to 10M+ AIG nodes in many computations

16. And-Inverter Graph (AIG) Definition and Examples
AIG is a Boolean network composed of two-input ANDs and inverters.
cdab 00 01 11 10 1
F(a,b,c,d) = ab + d(ac’+bc) b c a d
6 nodes
4 levels
F(a,b,c,d) = ac’(b’d’)’ + c(a’d’)’ = ac’(b+d) + bc(a+d)
cdab 00 01 11 10 1 a c b d
7 nodes
3 levels

17. Three Simple Tricks Structural hashing Complemented edges
Makes sure AIG is stored in a compact form
Is applied during AIG construction
Propagates constants
Makes each node structurally unique
Complemented edges
Represents inverters as attributes on the edges
Leads to fast, uniform manipulation
Does not use memory for inverters
Increases logic sharing using DeMorgan’s rule
Memory allocation
Uses fixed amount of memory for each node
Can be done by a simple custom memory manager
Even dynamic fanout manipulation is supported!
Allocates memory for nodes in a topological order
Optimized for traversal in the same topological order
Small static memory footprint for many applications
Computes fanout information on demand a b c d
Without hashing a b c d
With hashing

18. AIG: A Unifying Representation
An underlying data structure for various computations
Rewriting, resubstitution, simulation, SAT sweeping, induction, etc are based on the same AIG manager
A unifying representation for the whole flow
Synthesis, mapping, verification use the same data-structure
Allows multiple structures to be stored and used for mapping
The main circuit representation in ABC

19. SAT-based Methods
Nowadays, most of the hard problems are formulated and solved using Boolean satisfiability
Resubstitution, decomposition, delay/area optimization, etc
(and also technology mapping, detailed placement, routing, etc)
Heuristic solutions are often based on exact minimum results computed for small problem instances
For example, technology mapping for a small multi-output subject graph (up to 50 nodes) can be solved exactly in a short time
A robust problem formulation is as important as a fast SAT solver
Don’t-cares can be efficiently used during synthesis without computing them

20. Terminology Logic function (e.g. F = ab+cd) Logic network
Variables (e.g. b)
Minterms (e.g. abcd)
Cube (e.g. ab)
Logic network
Primary inputs/outputs
Logic nodes
Fanins/fanouts
Transitive fanin/fanout cone
Cut and window
Primary inputs
Primary outputs
Fanins
Fanouts
TFO
TFI

21. Don’t-Care-Based Optimization
Definition
A window for a node in the network is the context, in which its functionality is considered
A window includes
k levels of the TFI
m levels of the TFO
all re-convergent paths captured in this scope
Window POs
Window PIs
k = 3
m = 3

22. Constructing Boolean Relation Characterizing Node Functionality1
Construction steps:
Collect candidate divisors di of node n
Divisors are not in the TFO of n
Their support is a subset of that of node n
Duplicate the window of node n
Use the same set of input variables
Use a different set of output variables
Add inverter for node n in one copy
Create comparator for the outputs
Set the comparator to 1
This is the care set of node n
Convert all gates to CNF … d2 n n d1
How the relation is used:
Function n = F(d1, d2, …) belongs to the relation iff n can be implemented as a gate with function F in terms of divisors d1, d2, …
SAT solver is used to derive different functions F that can be used at the node X

23. Synthesis with Choices
Traditional synthesis explores a sequence of netlist snapshots
Modern synthesis allows for snapshots to be mixed-and-matched
This is achieved by computing structural choices
Synthesis D1 D2 D3 D4
Synthesis with choices D1
HAIG D4 D2 D3

24. Choice Computation Input is several versions of the same netlist
Example: area- and delay-optimized versions
Output is netlist with “choice nodes”
Fanins of a choice node are functionally equivalent nodes
Structural choices are used by the technology mapper to mix-and-match parts of the netlist, leading to better results
Computation
Combine netlists into one netlist (share inputs, append outputs)
Detect all pairs of equivalent nodes in the netlist (SAT seeping)
Record pairs of nodes proved equal to the SAT solver
Re-hash the netlist with the equivalences while creating choice nodes

25. Technology Mapping Input: A Boolean network (And-Inverter Graph)
Output: A netlist of K-LUTs implementing AIG and optimizing some cost function a b c d f e a b c d e f
Technology
Mapping
The subject graph
The mapped netlist

26. Modern Technology Mapping
Unification of all types of mappers
Standard cells, LUTs, programmable cells, etc
Using structural choices in all mappers
State-of-the-art heuristics use two good cuts at a node
Several flavors of SAT-based mapping are being developed
Currently SAT is limited to post-processing/optimization
Also used to pre-compute optimal results for small functions
May appear in the main-stream mappers in the future

27. Formal Verification Goal Formal vs. “informal” Difficulties
Making sure the design performs according to the spec
Formal vs. “informal”
Simulation is often not enough
Bounded verification is important but often not enough
Difficulties
Dealing with real designs
Modeling sequential logic (initialization, clock domains, etc)
Modeling the environment (need support for constraints)
Dealing with very large problems (need robust abstraction)
Industrial adoption is hindered by lack of understanding how to apply formal and by weakness of the tools
Two aspects of formal
Front-end (modeling)
Back-end (solving)
We will be mostly talking about the backend

28. Sequential Miter Equivalence checking Miter Equivalence checking
A sequential logic circuit
The result of modeling by frontend
To be solved by backend
Equivalence checking
Miter contains two copies of the design (golden and implementation)
Model checking
Miter contains one copy of the design and a property to be verified
The goal is to transform the miter presented as a sequential AIG, and prove that the output is constant 0 D2 D1
Equivalence checking D1
Property checking p

29. Outcomes of Verification
Success
The property holds in all reachable states
Failure
A finite-length counter-example (CEX) is found
Undecided
A limit on resources (such as runtime) is reached

30. Certifying Verification
How do we know that the answer produced by a verification tool is correct?
If the result is “SAT”, re-run the resulting CEX to make sure that it is valid
If the result is “UNSAT”, an inductive invariant can be generated and checked by a third-party tool

31. Inductive Invariant
An inductive invariant is a Boolean function in terms of register variables, such that
It is true for the initial state(s)
It is inductive
assuming that it holds in one (or more) time-frames allows us to prove it in the next time-frame
It does not contain “bad states” where property fails
State space
Bad
Invariant
Reached
Init

32. Verification Engines Bug-hunters (“informal”) Provers (“formal”)
random simulation
bounded model checking (BMC)
hybrids of the above two (“semi-formal”)
Provers (“formal”)
K-step induction, with or without uniqueness constraints
BDDs (exact reachability)
Interpolation (over-approximate reachability)
Property directed reachability (over-approximate reachability)
Interval property checking
Transformers
Combinational synthesis
Retiming
etc

33. Integrated Verification Flow
Deriving logic for gates or RTL
Modeling clocks, multi-phase clocking
Representing initialization logic, etc
Structural hashing, sequential cleanup, etc
Applying engine sequences (concurrently)
Using abstraction, speculation, etc
Trying to prove or find a bug with high resource limits
Creating sequential miter
Initial simplification
Progressive solving
Last-gasp solving

34. ABC in Design Flow System Specification RTL Verification ABC
Logic synthesis
Technology mapping
Physical synthesis
Manufacturing

35. Summary Introduced logic synthesis
Described representations and algorithms
Reviewed recent work

36. ABC Resources Tutorial Complete source code Windows binary
R. Brayton and A. Mishchenko, "ABC: An academic industrial-strength verification tool", Proc. CAV'10, LNCS 6174, pp
Complete source code
Windows binary

37. Abstract
This talk will review the development of logic synthesis from manipulating small Boolean functions using truth tables, through the discovery of efficient heuristic methods for sum-of-product minimization and algebraic factoring applicable to medium-sized circuits, to the present-day automated design flow, which can process digital designs with millions of logic gates. The talk will discuss the main computation engines and packages used in logic synthesis, such as circuit representation in the form of And-Inverter-Graphs, recent improvements to the traditional minimization and factoring methods, priority-cut-based technology mapping into standard-cells and lookup-tables, and don't-care-based optimization using Boolean satisfiability.  We will also discuss the importance of formal verification for validating the results produced by the synthesis tools, and the deep synergy between algorithms and data-structures used in synthesis and verification. In the course of this talk, the presenter will share his 14-year experience of being part of an academic research group with close connections to companies in Silicon Valley, both design houses and CAD tool vendors. 

38. Bio
Alan Mishchenko graduated from Moscow Institute of Physics and Technology, Moscow, Russia, in 1993, and received his Ph.D. degree from Glushkov Institute of Cybernetics, Kiev, Ukraine, in In 2002, Alan started at University of California at Berkeley as an Assistant Researcher and, in 2013, he was promoted to a Full Researcher. Alan shared the D.O. Pederson TCAD Best Paper Award in 2008 and the SRC Technical Excellence Award in 2011 for work on ABC. His research interests are in developing efficient methods for logic synthesis and verification.