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Faster Logic Manipulation for Large Designs Alan Mishchenko Robert Brayton University of California, Berkeley.

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Presentation on theme: "Faster Logic Manipulation for Large Designs Alan Mishchenko Robert Brayton University of California, Berkeley."— Presentation transcript:

1 Faster Logic Manipulation for Large Designs Alan Mishchenko Robert Brayton University of California, Berkeley

2 2 Outline Motivation Motivation Simple, local, iterative computation Simple, local, iterative computation Millions of 6-16 input functions (“small practical functions” = SPFs) Millions of 6-16 input functions (“small practical functions” = SPFs) Runtime / memory / quality can be improved Runtime / memory / quality can be improved Choosing the canonical form Choosing the canonical form Historic viewpoint Historic viewpoint Disjoint-support decomposition (DSD) Disjoint-support decomposition (DSD) DSD manager DSD manager Impact on computations Impact on computations Experimental results Experimental results Statistics of DSD functions Statistics of DSD functions Runtime improvements Runtime improvements Typical DSD structures Typical DSD structures Conclusions Conclusions

3 3 Disjoint Support Decomposition Primitive gates Primitive gates Const0 Const0 AND AND XOR XOR PRIME PRIME 2:1 MUX 2:1 MUX Majority Majority a b c de fghik

4 4 References Canonical form Canonical form R. L. Ashenhurst, “The decomposition of switching functions”. Computation Lab, Harvard University, 1959, Vol. 29, pp. 74-116. R. L. Ashenhurst, “The decomposition of switching functions”. Computation Lab, Harvard University, 1959, Vol. 29, pp. 74-116. Computation from cofactors Computation from cofactors V. Bertacco and M. Damiani, "Disjunctive decomposition of logic functions," Proc. ICCAD ‘97, pp. 78-82. V. Bertacco and M. Damiani, "Disjunctive decomposition of logic functions," Proc. ICCAD ‘97, pp. 78-82. Computation from cofactors (corrections) Computation from cofactors (corrections) Y. Matsunaga, "An exact and efficient algorithm for disjunctive decomposition", Proc. SASIMI '98, pp. 44-50. Y. Matsunaga, "An exact and efficient algorithm for disjunctive decomposition", Proc. SASIMI '98, pp. 44-50. Alternative computations Alternative computations T. Sasao and M. Matsuura, "DECOMPOS: An integrated system for functional decomposition," Proc. IWLS ’98, pp. 471-477. T. Sasao and M. Matsuura, "DECOMPOS: An integrated system for functional decomposition," Proc. IWLS ’98, pp. 471-477. S.-I. Minato and G. De Micheli, “Finding all simple disjunctive decompositions using irredundant sum-of-products forms”. Proc. ICCAD’98, pp. 111-117. S.-I. Minato and G. De Micheli, “Finding all simple disjunctive decompositions using irredundant sum-of-products forms”. Proc. ICCAD’98, pp. 111-117. Boolean operations Boolean operations S. Plaza and V. Bertacco, "Boolean operations on decomposed functions", Proc. IWLS ’05. S. Plaza and V. Bertacco, "Boolean operations on decomposed functions", Proc. IWLS ’05. Applications in synthesis and mapping Applications in synthesis and mapping A. Mishchenko, R. K. Brayton, and S. Chatterjee, "Boolean factoring and decomposition of logic networks", Proc. ICCAD'08, pp. 38-44. A. Mishchenko, R. K. Brayton, and S. Chatterjee, "Boolean factoring and decomposition of logic networks", Proc. ICCAD'08, pp. 38-44.

5 5 Timeline of (Canonical) Forms Truth tables (TTs) (< 1980) Truth tables (TTs) (< 1980) Sums-of-products (SOPs) (1980-1990) Sums-of-products (SOPs) (1980-1990) Binary decision diagrams (BDDs) (1990-2000) Binary decision diagrams (BDDs) (1990-2000) And-inverter graphs (AIGs) and truth tables (2000-2012) And-inverter graphs (AIGs) and truth tables (2000-2012) Disjoint-support decompositions (DSDs) (> 2012) Disjoint-support decompositions (DSDs) (> 2012) For small practical functions (SPFs) only For small practical functions (SPFs) only

6 6 DSDs vs BDDs vs TTs for SPFs TTs dominate BDDs in terms of memory and runtime TTs dominate BDDs in terms of memory and runtime TTs and BDDs are equally (in)convenient for detecting Boolean properties TTs and BDDs are equally (in)convenient for detecting Boolean properties DSDs take less memory/runtime than BDDs/TTs for pratical functions of K inputs (8 < K < 16) DSDs take less memory/runtime than BDDs/TTs for pratical functions of K inputs (8 < K < 16) DSDs explicitly represent Boolean properties DSDs explicitly represent Boolean properties Symmetry, unateness, NPN canonicity, decomposability, etc Symmetry, unateness, NPN canonicity, decomposability, etc Very important for practical applications! Very important for practical applications!

7 7 DSD Manager Similar to BDD manager Similar to BDD manager Maintains canonical forms Maintains canonical forms Performs Boolean operations Performs Boolean operations Employs computed table Employs computed table Different from BDD manager Different from BDD manager Different data structure Different data structure Different normalization rules Different normalization rules More reusable computed table More reusable computed table

8 8 Primitives of DSD Manager One constant 0 node One constant 0 node One primary input node n One primary input node n Multi-input AND and XOR nodes with ordered fanins Multi-input AND and XOR nodes with ordered fanins Three-input MUX nodes Three-input MUX nodes Multi-input PRIME nodes Multi-input PRIME nodes Non-decomposable functions Non-decomposable functions

9 9 Canonicity of DSDs Propagating inverters Propagating inverters AND(!a, !XOR(b, c))  AND(n, XOR(n, n)) AND(!a, !XOR(b, c))  AND(n, XOR(n, n)) Collapsing operators Collapsing operators AND(a, AND(b, !AND(c, d))  AND(n, n, !AND(n, n)) AND(a, AND(b, !AND(c, d))  AND(n, n, !AND(n, n)) Ordering fanins of AND/XOR Ordering fanins of AND/XOR Use support size Use support size If there is a tie, AND precedes XOR precedes MUX precedes PRIME. If there is a tie, AND precedes XOR precedes MUX precedes PRIME. If there is a tie, a non-inverted fanin precedes a inverted fanin. If there is a tie, a non-inverted fanin precedes a inverted fanin. If there is a tie, the fanins’ fanins are ordered and compared in their selected order If there is a tie, the fanins’ fanins are ordered and compared in their selected order If the recursive comparison fails to produce a unique order, the fanins’ DSD structures are isomorphic and therefore their order is immaterial. If the recursive comparison fails to produce a unique order, the fanins’ DSD structures are isomorphic and therefore their order is immaterial. Unifying variables Unifying variables AND(a, XOR(b, c), MUX(d, e, f))  AND(n, XOR(n, n), MUX(n, n, n)) AND(a, XOR(b, c), MUX(d, e, f))  AND(n, XOR(n, n), MUX(n, n, n))

10 10 Boolean Properties of SPFs (industrial benchmarks)

11 11 Boolean Properties of SPFs (public benchmarks)

12 12 LUT Structure Mapping Runtime

13 13 Typical DSD Structures !a = NOT( a ) (ab) = AND( a, b ) [ab] = XOR( a, b ) = MUX( a, b, c )

14 14 Conclusion (Re)invented DSD (Re)invented DSD Canonical form, which exposes Boolean properties Canonical form, which exposes Boolean properties Introduced a DSD package Introduced a DSD package An alternative to a BDD package for SPFs An alternative to a BDD package for SPFs Discussed preliminary experimental results Discussed preliminary experimental results Exciting future work is waiting to be done! Exciting future work is waiting to be done!

15 15 Abstract When logic transformations, such as circuit restructuring, technology mapping, and post-mapping optimization, are repeatedly applied to large hardware designs, millions of relatively small (6-16 input) Boolean functions have to be efficiently manipulated. This paper focuses on a novel representation of these small functions, in terms of their disjoint-support decomposition (DSD) structures. A new DSD manipulation package is developed, which allows for faster logic manipulation compared to known methods. When logic transformations, such as circuit restructuring, technology mapping, and post-mapping optimization, are repeatedly applied to large hardware designs, millions of relatively small (6-16 input) Boolean functions have to be efficiently manipulated. This paper focuses on a novel representation of these small functions, in terms of their disjoint-support decomposition (DSD) structures. A new DSD manipulation package is developed, which allows for faster logic manipulation compared to known methods.


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