1. Robert Brayton Alan Mishchenko Niklas Een
AIG Primer
Robert Brayton Alan Mishchenko Niklas Een
UC Berkeley

2. Overview A unifying representation AIG representation AIG manipulation
Definition
Sequential AIGs
Main differences
Rewriting
AIG manager
AIG manipulation
Basic AIG operations
Topological traversal / levelized orders
Working with equivalences
Working with choices
Overview of several AIG-based algorithms
Future developments

3. AIG: A Unifying Representation
An underlying data structure for various computations
Representing both local and global functions
Used in rewriting, resubstitution, simulation, SAT sweeping, induction, etc
A unifying representation for the whole flow
Synthesis, mapping, verification pass around AIGs
Allows multiple structures to be stored for mapping
The main functional representation in ABC
Foundation of ‘contemporary’ logic synthesis
Source of ‘signature features’ (speed, scalability, etc)

4. AIG Definition and Examples
AIG is a Boolean network composed of two-input ANDs and inverters
cdab 00 01 11 10 1
F(a,b,c,d) = ab + d(ac’+bc) b c a d
6 nodes
4 levels
F(a,b,c,d) = ac’(b’d’)’ + c(a’d’)’ = ac’(b+d) + bc(a+d)
cdab 00 01 11 10 1 a c b d
7 nodes
3 levels

5. Sequential AIGs
Sequential networks have memory elements in addition to logic nodes
Memory elements are modeled as D-flip-flops
Initial state {0,1,x} is assumed to be given
Several ways of representing sequential AIGs
Additional PIs and POs in the combinational AIG
Additional register nodes with sequential structural hashing
Sequential synthesis (in particular, retiming) annotates registers with additional information
Takes into account register type and its clock domain

6. Three Simple Tricks Structural hashing Complemented edges
Makes sure AIG is always stored in a compact form
Is applied during AIG construction
Propagates constants
Ensures each node is structurally unique
Complemented edges
Represents inverters as attributes on the edges
Leads to fast, uniform manipulation
Does not use memory for inverters
Leads to efficient structural hashing
Memory allocation
Uses fixed amount of memory for each node
Can be done by a simple custom memory manager
Even dynamic fanout manipulation is supported!
Allocates memory for nodes in a topological order
Optimized for traversal in the same topological order
Small static memory footprint for many applications a b c d
Without hashing a b c d
With hashing

7. AIG Rewriting
AIG rewriting aims at minimizing the number of AIG nodes without increasing the number of AIG levels
Pre-computing AIG subgraphs
Consider function f = abc
Rewriting AIG subgraphs
Rewriting node A a b c A
Subgraph 1 b c a A
Subgraph 2 a b c
Subgraph 1 b c a
Subgraph 2 a c b
Subgraph 3 
Rewriting node B b c a B
Subgraph 2 a b c B
Subgraph 1  a b c
In both cases 1 node is saved

8. Rules of the AIG Manager
Only the following four types of AIG objects allowed:
primary inputs, flop outputs
internal AND nodes
primary outputs, flop inputs
exactly one constant node
Only two-input AND nodes allowed: no single-input buffers, etc
AIG is always structurally hashed
for each AND node, no other AND node has the same fanins
fanins are fanin node IDs, together with their complemented attributes
constant fanins of internal nodes are propagated
Additionally the following invariants are satisfied
each AND node has a fanout (no internal dangling nodes)
all objects are stored in a topological order
the constant 1 (or 0) node has always number 0 in the object list
by default, there is no fanout representation

9. AIG Manipulation AIG operations Structural analysis (see next slide)
building new nodes (Aig_And)
performing Boolean operations (Aig_Or, Aig_Xor, etc)
replacing one node by another (Aig_ObjReplace)
propagating constants (Aig_ObjReplace)
Structural analysis (see next slide)
Specialized computations (too many to list)
Example: duplication
There are 10+ duplicators, including a plain vanilla one
The duplicated AIG is also structurally hashed
If repeated duplication leads to fewer nodes, it means
the original AIG was not strictly hashed
the original AIG had duplicated nodes
In other words, one of the rules is violated
should never happen for the AIG manager to work correctly

10. Traversals and Orders
AIG nodes are topologically ordered (convenient!)
However, this order may not be the best…
Sequential simulation can be made 2x faster and 10x less memory-intensive by changing the default topological order
Levelized orders can be computed
Vec_Vec_t * Aig_ManLevelize( Aig_Man_t * p );
Returns a vector of vectors: for each level, nodes on that level
Levelized orders are useful
When duplicating AIG manager with choices
When doing AIG partitioning
When performing SAT sweeping

11. Working with Equivalences
Array (pMan->pReprs) is used to store equivalences of AIG objects
Each node, if equivalent to another, points to it
The representative of a node always has a lower ID than the node
Only primary inputs, flop outputs, and internal AND nodes can have a representative listed
in other words, primary outputs and flop inputs are just structural boxes, which are not considered
Procedures to create equivalences
void Aig_ManReprStart( Aig_Man_t * p, int nIdMax );
void Aig_ManReprStop( Aig_Man_t * p );
void Aig_ObjCreateRepr( Aig_Man_t * p, Aig_Obj_t * pNode1, Aig_Obj_t * pNode2 );
Procedures that use equivalences
Merging nodes proved equivalent:
Aig_Man_t * Aig_ManDupRepres( Aig_Man_t * p );

12. Working with Choices
A choice (or a choice node) is an equivalence class of AIG objects:
In addition to the array (pMan->pReprs) used to store equivalences, nodes belonging to a choice node form a single-linked linked list
Important:
Representative of each class has the smallest ID among all the nodes in the class
AIG nodes belonging to the same choice cannot be fanins/fanouts of each other
In the levelized orders, the level of a representive node is defined as the max of the levels of the nodes belong to the choice node
Deriving AIG with choices from representatives after SAT sweeping:
Aig_Man_t * Dch_DeriveChoiceAig( Aig_Man_t * pAig );

13. Using AIG Package the fine print at the bottom of ABC webpage
Download the latest snapshot of ABC from
Compile the code in "abc\src\aig\aig", "abc\src\aig\saig", and "abc\src\misc\vec" as a static library.
Link the library to the project.
Add #include "saig.h".
Start the AIG package using Aig_ManStart().
Assign primary inputs using Aig_ObjCreatePi().
Assign register outputs using Aig_ObjCreatePi().
(it is important to create all PIs first, before creating register outputs).
Construct AIG in the topological order using Aig_And(), Aig_Or(), Aig_Not(), etc.
If constant-0/1 AIG nodes are needed, use Aig_ManConst0() or Aig_ManConst1()
Create primary outputs using Aig_ObjCreatePo().
Create register inputs using Aig_ObjCreatePo().
(it is important to create all POs first, before creating register inputs).
Set the number of registers by calling Aig_ManSetRegNum().
Remove dangling AIG nodes (produced by structural hashing) using Aig_ManCleanup().
Call the consistency checking procedure Aig_ManCheck().
Dump AIG into a file using the new BLIF dumper Saig_ManDumpBlif().
Alternatively, manipulate, synthesize, transform the resulting AIG.
For each object in the design annotated with the constructed AIG node (pNode), remember its AIG node ID by calling Aig_ObjId( Aig_Regular(pNode) ). To check whether the corresponding AIG node is complemented use Aig_IsComplement(pNode).
Quit the AIG package using Aig_ManStop().
The above process should not produce memory leaks.

14. Overview of AIG-Based Algorithms
Tech-independent AIG-based synthesis
Balancing, rewriting, refactoring, resubstitution, etc
Computation of structural choices
Technology mapping
AIG is the subject graph
Tech-dependent synthesis (resynthesis)
AIG is the underlying functionality representation
Now: only local functions and the SAT solver
Future: will also represent the mapped network with boxes
Other applications
Formal verification
Sequential simulation for power estimation
etc (too many to list)

15. Future of AIGs AIGs will continue to proliferate - at least in ABC
New AIG package (src/aig/gia) is responsible for the recent improvements in runtime, memory
And this is not the limit
Development of dedicated AIG-based procedures, such as SAT solving, becomes the first priority
Continuing to reduce memory and runtime
Making various AIG computations box-aware
Extensively using AIG-based don’t-cares computation
A better integration of AIGs with other parts of the system can be achieved
Resulting in fewer internal duplications, transformations, etc