1. Wenlong Yang Lingli Wang State Key Lab of ASIC and System Fudan University, Shanghai, China Alan Mishchenko Department of EECS University of California, Berkeley 1 Lazy Man’s Logic Synthesis

2.  Introduction  Previous Work  Lazy Man’s Logic Synthesis(LMS)  Experimental Results  Conclusion & Future Work 2

3.  Goal of logic synthesis: Deriving a circuit or improving an available circuit  We proposed a “Lazy” approach to reuse optimal structures derived by other synthesis tools based on a pre-computed library AIG A Function with N variables Other tools LMS precomputed library 3

4.  Introduction  Previous Work  Lazy Man’s Logic Synthesis(LMS)  Experimental Results  Conclusion 4

5.  Logic synthesis based on precomputed library have been proposed in several papers, but they are all different from LMS: Previous work Precompute structures in terms of LUTs [Kennings, IWLS, 2010 ] Didn't use preexisting benchmarks or tools [Bjesse, ICCAD, 2004 ] Look at only 4-5 input functions [Li, IWLS, 2011 ] Only compute multiple structure choices [Chatterjee, TCAD, 2006 ] LMS Precompute structures in terms of AIGs Use public benchmarks and existing tools Look at 6-16 input functions Store many equivalent structures 5

6. For each node Compute several k-input cuts Perform delay-optimal tree balancing of the SOP Select the best one to replace the current structure. An AIG subgraph found in benchmark s27.blif where SOP balancing loses to the proposed approach F = !c*!b + !c*aF’ = !c*!(b*!a) 6

7.  Introduction  Previous Work  Lazy Man’s Logic Synthesis(LMS)  Equivalence Classes  Library Representation/Construction  Implementation  Experimental Results  Conclusion 7

8.  LMS is based on collecting, storing, and re-using circuit structures of Boolean functions with 6-16 input variables.  The total number of completely-specified Boolean functions of N variables is 2 ^( 2 ^N).  Experiments shows that even for the practical functions, this number can be very large. To reduce the number and memory need to store functions in a library, a canonical form is used to break them into Equivalence Classes. 8

9.  Two functions are NPN-equivalent if one of them can be obtained from the other by negation and/or permutation of the inputs and outputs. Complete NPN canonical form is not affordable to LMS Drawbacks of NPN computation: Time-consuming Complicated 9

10.  The idea is to order the input variables and the polarities of inputs/outputs using the number of positive minterms and cofactors w.r.t. each variable. Input: TruthTable F 1. Determine the polarity of F by the number of 1’s in TruthTable 2. Determine the polarity of each variable by the number of 1s in the negative cofactor w.r.t. each variable 3. Sort input variables by the number of 1s in their negative cofactors and permute inputs accordingly Output: canonicized TruthTable F A reasonable trade-off between accuracy and speed 10

11.  An N-input library contains functions up to N variables.  Structures of all functions are represented as a shared AIG  Each output of the AIG is the root node of one logic structure.  When a library is loaded, the following actions are performed:  A hash table is created to hash the outputs by its semi-canonical form.  For each structure, the area and pin-to-output delays are computed and stored. 11

12. Example of using pin-to-output delays to compute structure delay Suppose arrival time: {3, 2, 4, 5, 2, 3, 1} Pin-to-output delay: {3, 3, 3, 5, 5, 4, 1} + {6, 5, 7, 10, 7, 7, 2} = If one structure’s pin-to-output delay is worse than another with respect to every input, the structure is dominated. 12

13.  LUT mapper if in ABC is used as a structural cut browser to generate K- input cuts whose logic structures are added to the library. Input: Cut C 1. If cut C does not meet the requirements return 2. Compute Boolean function F of cut C as a truthtable 3. Compute the semi-canonical form of F 4. Rebuild the structure of the cut in the library 5. If ( the structure already exists or is dominated ) return 6. Add a new primary output to store the structure in the hash table 13

14. Input: And-Inverter Graph  For each node, in a topological order  Compute several K-input cuts  For each cut ▪ Compute truth table ▪ Look up in the library ▪ If there is no structure for this function  Mark the cut to ensure it is not selected as best cut ▪ Else if the best structure found leads to smaller AIG level  Save the cut as the best cut  If there is an improvement in level, update AIG 14

15.  The LMS algorithm is implemented in ABC. The LUT mapper if in ABC is used as:  (a) A cut browser for computing the libraries  (b) A mapper in the case study on AIG level minimization Commands related to library construction: rec_start: Starts the LMS recorder. rec_add: Add structures from benchmarks rec_filter: Removes the structures with less frequency rec_merge: Merges two previously computed libraries rec_ps: Prints statistics for the currently loaded library rec_use: Transforms the internal library to the current network in ABC rec_stop: Deletes the current library. Commands used to perform LMS mapping: if –y –K -C -y enables level optimization by LMS -K is the cut size -C is the number of cuts used at each node 15

16.  Introduction  Previous Work  Lazy Man’s Logic Synthesis(LMS)  Experimental Results  Library Coverage  6-input Library  Optimize Delay After LUT Mapping  Conclusion 16

17.  This experiment was performed to show that LMS has practical memory requirements for functions up to 12 inputs.  Semi-canonical classes of all functions appearing in the cuts of the benchmark circuits without synthesis, were collected and the frequency of their appearance was recorded. occurrence frequency ~2 M classes in total ~740 K classes for 90% functions ~400MB for truth tables 17 Function #

18.  The goal of this experiment is to derive a 6-input library used in the following case study of AIG level minimization.  The following ABC scripts are used to collect structures: read file; st; rec_add; dc2; rec_add; if -K 8; bidec; st; rec_add; if -K 8; mfs; st; rec_add; if -K 8; bidec; st; rec_add; if -g -K 6; st; rec_add; InputsClasses #Structures #Ratio 2331.00 332882.75 42,43012,6735.22 598,208471,9734.81 61,148,5565,202,9244.53 Total1,249,2295,687,6614.55 Statistics of the precomputed 6-input library ~77MB AIGER file 18

19.  Two sets of benchmarks are used in this paper: 20 MCNC benchmarks and 10 large Altera benchmarks.  LUT mapping was performed by the following scripts:  Map: st; resyn2; if -K 4 or 6  MapC: st; resyn2; dch -f; if -K 4 or 6  SOPBC: st; if -gm -K 6; st; resyn2; dch -f; if -K 4 or 6  LMSC: st; if -ym -K 6; st; resyn2; dch -f; if -K 4 or 6  Benchmarks were run on a workstation with a Intel Xeon Quad Core CPU and 256 GBytes RAM (~4GB used for the experiment)  The resulting networks were verified by command cec in ABC. 19

20. LMSC reduced delay by 37% with an area increase of 13% 20

21. LMSC reduced delay by 26% with an area increase of 13% 21

22. Design4-LUT level4-LUT count6-LUT level6-LUT count MapMapCSOPBCLMSCMapMapCSOPBCLMSCMapMapCSOPBCLMSCMapMapCSOPBCLMSC alu477776947017027145555503525520532 apex288888718678748906666691683728711 b14212017 176117711913184913 10111275126315171442 b1522 21 314731033186323315 14132119221122552419 b1731 2726967695079527957021 16 6510635666676670 b20232219 369235873886382915 12 2679261930703044 b2123222019376836123847390815 11122701257731143115 b2223 19 542352805693572915 12113985384746384677 clma13 12 401640084189415099882975289431453246 des666612281257124912735554824862866953 elliptic88884314324424436666317 327333 ex5p66664714624724815454351382378408 frisc20 1916227922612332227913121191807181118831948 i1014 13127467417437419999598608575583 pdc9888192620471925207577671428135016191416 s385849988402139783985398066662720280228162831 s537866554594514704684444356355369358 seq66669469359489415555685668707696 spla9998189918031860192877661414136114451455 tseng13 12107568007438098866648694689731 Raito 1.000.990.920.901.00 1.021.031.000.990.900.881.00 1.071.08 4 -LUTs: LMSC reduced delay by 10% with an area increase of 3% 6-LUTs: LMSC reduced delay by 12% with an area increase of 8% 22

23.  A new method to harvest and re-use circuit structures produced by different tools on benchmark circuits  The “lazy” approach is made practical by  A semi-canonical form to reduce the number of equivalence classes  Using AIGs to store precomputed libraries in memory and on disk  Using truth tables to manipulate Boolean functions  As the case-study, the proposed approach was applied to improve delay after FPGA mapping  For industrial benchmarks, compared to SOP balancing,  the delay was reduced by 17% ( 18% ) for LUT 4 (LUT 6 )  the area penalty was 2% ( 5% ) 23

24.  Improving implementation  Reducing memory by using a low-memory AIG  Building libraries in terms of multi-input gates  Filtering libraries based on their performance  Giving the user control over the area increase  Continuing experiments  Performing case studies with larger functions  Evaluating delay improvements after P&R 24

25. Authors' E-mail:  Wenlong Yang allanwin@hotmail.comallanwin@hotmail.com  Lingli Wang llwang@fudan.edu.cnllwang@fudan.edu.cn  Alan Mishchenkoalanmi@eecs.berkeley.edualanmi@eecs.berkeley.edu 25

26. Deriving a circuit for a Boolean function or improving an available circuit are typical tasks solved by logic synthesis. Numerous algorithms in this area have been proposed and implemented over the last 50 years. This paper presents a "lazy” approach to logic synthesis based on the following observations: (a) optimal or near-optimal circuits for many practical functions are already derived by the tools, making it unnecessary to implement new algorithms or even run the old ones repeatedly; (b) larger circuits are composed of smaller ones, which are often isomorphic up to a permutation/negation of inputs/outputs. Experiments confirm these observations. Moreover, a case-study shows that logic level minimization using lazy man’s synthesis improves delay after LUT mapping into 4- and 6-input LUTs, compared to earlier work on high-effort delay optimization.